Inventor · disambiguated record
Paul M. Steinmetz
Also filed as: STEINMETZ PAUL · STEINMETZ PAUL M · STEINMETZ PAUL MICHAEL
15 granted patents·2 pending applications·75 citations·filing 2005–2017
91Inventor score
Top patents by PatentIndex Score
17 records- 0184US7523265B2Systems and arrangements for promoting a line to exclusive in a fill buffer of a cacheIBM·Filed 2005·Granted Apr 21, 2009·14 cites·20 claims
- 0283US8122399B2Compiler for closed-loop 1×N VLSI designBOWERS BENJAMIN J·Filed 2008·Granted Feb 21, 2012·10 cites·11 claims
- 0382US8141016B2Integrated design for manufacturing for 1×N VLSI designCORREALE JR ANTHONY·Filed 2008·Granted Mar 20, 2012·13 cites·27 claims
- 0478US9558308B2Compiler for closed-loop 1×N VLSI designMENTOR GRAPHICS CORP·Filed 2014·Granted Jan 31, 2017·3 cites·16 claims
- 0576US7966598B2Top level hierarchy wiring via 1×N compilerIBM·Filed 2008·Granted Jun 21, 2011·9 cites·20 claims
- 0675US8887113B2Compiler for closed-loop 1xN VLSI designBOWERS BENJAMIN J·Filed 2012·Granted Nov 11, 2014·3 cites·14 claims
- 0773US8156458B2Uniquification and parent-child constructs for 1xN VLSI designBAKER MATTHEW W·Filed 2008·Granted Apr 10, 2012·9 cites·23 claims
- 0870US8136062B2Hierarchy reassembler for 1×N VLSI designSTEINMETZ PAUL M·Filed 2008·Granted Mar 13, 2012·7 cites·22 claims
- 0966US7752396B2Promoting a line from shared to exclusive in a cacheIBM·Filed 2008·Granted Jul 6, 2010·3 cites·6 claims
- 1060US7319578B2Digital power monitor and adaptive self-tuning power managementIBM·Filed 2005·Granted Jan 15, 2008·2 cites·15 claims
- 1158US7882385B2Reducing inefficiencies of multi-clock-domain interfaces using a modified latch bankIBM·Filed 2007·Granted Feb 1, 2011·1 cites·20 claims
- 1256US8132134B2Closed-loop 1×N VLSI design systemCORREALE JR ANTHONY·Filed 2008·Granted Mar 6, 2012·1 cites·21 claims
- 1351US8739086B2Compiler for closed-loop 1×N VLSI designBOWERS BENJAMIN J·Filed 2012·Granted May 27, 2014·0 cites·5 claims
- 1447US2010107130A11xn block builder for 1xn vlsi designIBM·Filed 2008·Application pending·0 cites
- 1541US2007038814A1Systems and methods for selectively inclusive cacheIBM·Filed 2005·Application pending·0 cites
- 1635US9201801B2Computing device with asynchronous auxiliary execution unitBOURY BECHARA F·Filed 2010·Granted Dec 1, 2015·0 cites·25 claims
- 1731US10541044B2Providing efficient handling of memory array failures in processor-based systemsQUALCOMM INC·Filed 2017·Granted Jan 21, 2020·0 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →