Inventor · disambiguated record
Bert Sullam
Also filed as: SULLAM BERT · SULLAM BERT S
47 granted patents·6 pending applications·1,278 citations·filing 1994–2024
98Inventor score
Top patents by PatentIndex Score
53 records- 0198US8487655B1Combined analog architecture and functionality in a mixed-signal arrayKUTZ HAROLD·Filed 2010·Granted Jul 16, 2013·79 cites·21 claims
- 0298US8026739B2System level interconnect with programmable switchingCYPRESS SEMICONDUCTOR CORP·Filed 2007·Granted Sep 27, 2011·59 cites·20 claims
- 0396US9143134B1Combined analog architecture and functionality in a mixed-signal arrayCYPRESS SEMICONDUCTOR CORP·Filed 2013·Granted Sep 22, 2015·15 cites·20 claims
- 0496US7737724B2Universal digital block interconnection and channel routingCYPRESS SEMICONDUCTOR CORP·Filed 2007·Granted Jun 15, 2010·30 cites·16 claims
- 0596US6614320B1System and method of providing a programmable clock architecture for an advanced microcontrollerCYPRESS SEMICONDUCTOR CORP·Filed 2001·Granted Sep 2, 2003·140 cites·29 claims
- 0695US7076420B1Emulator chip/board architecture and interfaceCYPRESS SEMICONDUCTOR CORP·Filed 2001·Granted Jul 11, 2006·130 cites·26 claims
- 0794US8135884B1Programmable interrupt routing systemSULLAM BERT·Filed 2010·Granted Mar 13, 2012·27 cites·23 claims
- 0894US6967511B1Method for synchronizing and resetting clock signals supplied to multiple programmable analog blocksCYPRESS SEMICONDUCTOR CORP·Filed 2001·Granted Nov 22, 2005·67 cites·25 claims
- 0992US8476928B1System level interconnect with programmable switchingSULLAM BERT·Filed 2011·Granted Jul 2, 2013·8 cites·20 claims
- 1092US7308608B1Reconfigurable testing system and methodCYPRESS SEMICONDUCTOR CORP·Filed 2002·Granted Dec 11, 2007·88 cites·20 claims
- 1192US7023257B1Architecture for synchronizing and resetting clock signals supplied to multiple programmable analog blocksCYPRESS SEMICONDUCTOR CORP·Filed 2001·Granted Apr 4, 2006·68 cites·13 claims
- 1291US9325320B1System level interconnect with programmable switchingCYPRESS SEMICONDUCTOR CORP·Filed 2013·Granted Apr 26, 2016·6 cites·20 claims
- 1391US8601254B1Configurable reset pin for input/output portKUTZ HAROLD·Filed 2010·Granted Dec 3, 2013·22 cites·20 claims
- 1490US6950954B1Method and circuit for synchronizing a write operation between an on-chip microprocessor and an on-chip programmable analog device operating at different frequenciesCYPRESS SEMICONDUCTOR CORP·Filed 2001·Granted Sep 27, 2005·64 cites·20 claims
- 1590US6859884B1Method and circuit for allowing a microprocessor to change its operating frequency on-the-flyCYPRESS SEMICONDUCTOR CORP·Filed 2001·Granted Feb 22, 2005·74 cites·20 claims
- 1689US9553588B2System level interconnect with programmable switchingCYPRESS SEMICONDUCTOR CORP·Filed 2015·Granted Jan 24, 2017·4 cites·5 claims
- 1789US8125360B1On-chip calibration methodKUTZ HAROLD·Filed 2010·Granted Feb 28, 2012·11 cites·20 claims
- 1888US11105851B2Combined analog architecture and functionality in a mixed-signal arrayCYPRESS SEMICONDUCTOR CORP·Filed 2020·Granted Aug 31, 2021·2 cites·20 claims
- 1988US10097185B2System level interconnect with programmable switchingCYPRESS SEMICONDUCTOR CORP·Filed 2017·Granted Oct 9, 2018·3 cites·11 claims
- 2088US8643519B1On-chip calibration methodKUTZ HAROLD·Filed 2012·Granted Feb 4, 2014·9 cites·20 claims
- 2187US8482313B2Universal digital block interconnection and channel routingSNYDER WARREN·Filed 2011·Granted Jul 9, 2013·8 cites·22 claims
- 2287US5697789AMethod and system for aiding foreign language instructionSOFTRADE INTERNATIONAL INC·Filed 1994·Granted Dec 16, 1997·138 cites·26 claims
- 2386US8838852B1Programmable interrupt routing systemSULLAM BERT·Filed 2012·Granted Sep 16, 2014·8 cites·20 claims
- 2486US8598908B1Built in system bus interface for random access to programmable logic registersSULLAM BERT·Filed 2010·Granted Dec 3, 2013·11 cites·20 claims
- 2586US8112551B2Addressing scheme to allow flexible mapping of functions in a programmable logic arraySULLAM BERT·Filed 2010·Granted Feb 7, 2012·9 cites·20 claims
- 2685US7479913B1Configurable analog to digital converterCYPRESS SEMICONDUCTOR CORP·Filed 2007·Granted Jan 20, 2009·16 cites·19 claims
- 2783US5882202AMethod and system for aiding foreign language instructionSOFTRADE INTERNATIONAL·Filed 1996·Granted Mar 16, 1999·137 cites·35 claims
- 2882US10345377B2Combined analog architecture and functionality in a mixed-signal arrayCYPRESS SEMICONDUCTOR CORP·Filed 2018·Granted Jul 9, 2019·2 cites·20 claims
- 2981US9612987B2Dynamically reconfigurable analog routing circuits and methods for system on a chipSULLAM BERT·Filed 2010·Granted Apr 4, 2017·6 cites·19 claims
- 3081US8402313B1Reconfigurable testing system and methodPLEIS MATTHEW A·Filed 2007·Granted Mar 19, 2013·12 cites·20 claims
- 3179US10826499B2System level interconnect with programmable switchingCYPRESS SEMICONDUCTOR CORP·Filed 2019·Granted Nov 3, 2020·1 cites·5 claims
- 3278US9952282B1Combined analog architecture and functionality in a mixed-signal arrayCYPRESS SEMICONDUCTOR CORP·Filed 2015·Granted Apr 24, 2018·1 cites·20 claims
- 3377US10634722B1Combined analog architecture and functionality in a mixed-signal arrayCYPRESS SEMICONDUCTOR CORP·Filed 2019·Granted Apr 28, 2020·1 cites·25 claims
- 3475US8516025B2Clock driven dynamic datapath chainingSYNDER WARREN·Filed 2008·Granted Aug 20, 2013·9 cites·17 claims
- 3574US9448964B2Autonomous control in a programmable systemSULLAM BERT·Filed 2010·Granted Sep 20, 2016·4 cites·17 claims
- 3672US12261602B2Ultra-low power adaptively reconfigurable systemCYPRESS SEMICONDUCTOR CORP·Filed 2022·Granted Mar 25, 2025·0 cites·19 claims
- 3771US7555664B2Independent control of core system blocks for power optimizationCYPRESS SEMICONDUCTOR CORP·Filed 2006·Granted Jun 30, 2009·5 cites·20 claims
- 3869US8639850B1Addressing scheme to allow flexible mapping of functions in a programmable logic arraySULLAM BERT·Filed 2012·Granted Jan 28, 2014·2 cites·20 claims
- 3963US10516397B2System level interconnect with programmable switchingCYPRESS SEMICONDUCTOR CORP·Filed 2018·Granted Dec 24, 2019·0 cites·20 claims
- 4061US12470216B2System and method for configuring programmable analog blockCYPRESS SEMICONDUCTOR CORP·Filed 2023·Granted Nov 11, 2025·0 cites·20 claims
- 4160US2024385139A1Programmable sensorCYPRESS SEMICONDUCTOR CORP·Filed 2023·Application pending·0 cites
- 4256US9018979B2Universal digital block interconnection and channel routingCYPRESS SEMICONDUCTOR CORP·Filed 2013·Granted Apr 28, 2015·0 cites·20 claims
- 4356US2025258515A1Control system and methodCYPRESS SEMICONDUCTOR CORP·Filed 2024·Application pending·0 cites
- 4455US11533055B2Ultra-low power adaptively reconfigurable systemCYPRESS SEMICONDUCTOR CORP·Filed 2019·Granted Dec 20, 2022·0 cites·23 claims
- 4553US9880536B1Autonomous control in a programmable systemCYPRESS SEMICONDUCTOR CORP·Filed 2015·Granted Jan 30, 2018·0 cites·13 claims
- 4652US2017286344A1Dynamically Reconfigurable Analog Routing and Multiplexing Architecture on a System on a ChipCYPRESS SEMICONDUCTOR CORP·Filed 2017·Application pending·0 cites
- 4751US9564902B2Dynamically configurable and re-configurable data pathSYNDER WARREN·Filed 2007·Granted Feb 7, 2017·2 cites·20 claims
- 4850US2024394452A1Methods, devices and systems for analog circuit block operations configurable with memory-mapped entriesCYPRESS SEMICONDUCTOR CORP·Filed 2023·Application pending·0 cites
- 4949US8250249B1Processor independent line driving and receiving systemKAVAIYA GAURANG·Filed 2009·Granted Aug 21, 2012·0 cites·20 claims
- 5048US8686985B2Active liquid crystal display drivers and duty cycle operationSNYDER WARREN·Filed 2007·Granted Apr 1, 2014·0 cites·19 claims
Showing the top 50 of 53 patent records by PatentIndex Score.
Join the waitlist — get patent alerts
Get an alert when Bert Sullam files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →