Inventor · disambiguated record
Leith L. Johnson
Also filed as: JOHNSON LEITH · JOHNSON LEITH L
21 granted patents·2 pending applications·782 citations·filing 1991–2007
96Inventor score
Top patents by PatentIndex Score
23 records- 0195US6678811B2Memory controller with 1X/MX write capabilityHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Jan 13, 2004·119 cites·6 claims
- 0294US6073223AMemory controller and method for intermittently activating and idling a clock signal for a synchronous memoryHEWLETT PACKARD CO·Filed 1997·Granted Jun 6, 2000·132 cites·17 claims
- 0394US5987576AMethod and apparatus for generating and distributing clock signals with minimal skewHEWLETT PACKARD CO·Filed 1997·Granted Nov 16, 1999·131 cites·11 claims
- 0479US5287477AMemory-resource-driven arbitrationHEWLETT PACKARD CO·Filed 1991·Granted Feb 15, 1994·82 cites·10 claims
- 0578US7451249B2Method and apparatus for direct input and output in a virtual machine environment containing a guest operating systemHEWLETT PACKARD DEVELOPMENT CO·Filed 2006·Granted Nov 11, 2008·9 cites·39 claims
- 0677US7103793B2Memory controller having receiver circuitry capable of alternately generating one or more data streams as data is received at a data pad, in response to counts of strobe edges received at a strobe padHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Sep 5, 2006·18 cites·15 claims
- 0775US7103790B2Memory controller driver circuitry having a multiplexing stage to provide data to at least N-1 of N data propagation circuits, and having output merging circuitry to alternately couple the N data propagation circuits to a data pad to generate either a 1x or Mx stream of dataHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Sep 5, 2006·18 cites·14 claims
- 0873US6633965B2Memory controller with 1×/M× read capabilityFiled 2001·Granted Oct 14, 2003·15 cites·27 claims
- 0972US6889335B2Memory controller receiver circuitry with tri-state noise immunityHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted May 3, 2005·17 cites·42 claims
- 1063US6715014B1Module arrayHEWLETT PACKARD DEVELOPMENT CO·Filed 2000·Granted Mar 30, 2004·12 cites·10 claims
- 1163US5870573ATransistor switch used to isolate bus devices and/or translate bus voltage levelsHEWLETT PACKARD CO·Filed 1996·Granted Feb 9, 1999·43 cites·17 claims
- 1262US7624234B2Directory caches, and methods for operation thereofHEWLETT PACKARD DEVELOPMENT CO·Filed 2006·Granted Nov 24, 2009·2 cites·27 claims
- 1362US5274671AUse of output impedance control to eliminate mastership change-over delays in a data communication networkHEWLETT PACKARD CO·Filed 1991·Granted Dec 28, 1993·38 cites·16 claims
- 1459US8386702B2Memory controllerHEWLETT PACKARD DEVELOPMENT CO·Filed 2005·Granted Feb 26, 2013·1 cites·23 claims
- 1558US5257356AMethod of reducing wasted bus bandwidth due to slow responding slaves in a multiprocessor computer systemHEWLETT PACKARD CO·Filed 1991·Granted Oct 26, 1993·34 cites·15 claims
- 1657US5249297AMethods and apparatus for carrying out transactions in a computer systemHEWLETT PACKARD CO·Filed 1991·Granted Sep 28, 1993·32 cites·20 claims
- 1752US5689660AEnhanced peripheral component interconnect bus protocolHEWLETT PACKARD CO·Filed 1996·Granted Nov 18, 1997·29 cites·11 claims
- 1848US5928346AMethod for enhanced peripheral component interconnect bus split data transferHEWLETT PACKARD CO·Filed 1997·Granted Jul 27, 1999·22 cites·9 claims
- 1945US8782779B2System and method for achieving protected region within computer systemGILES CHRIS M·Filed 2007·Granted Jul 15, 2014·0 cites·14 claims
- 2044US5255373ADecreasing average time to access a computer bus by eliminating arbitration delay when the bus is idleHEWLETT PACKARD CO·Filed 1991·Granted Oct 19, 1993·16 cites·5 claims
- 2142US2007261059A1Array-based memory abstractionORTH JOSEPH F·Filed 2006·Application pending·0 cites
- 2242US2003110205A1Virtualized resources in a partitionable serverFiled 2001·Application pending·0 cites
- 2340US5961655AOpportunistic use of pre-corrected data to improve processor performanceHEWLETT PACKARD CO·Filed 1996·Granted Oct 5, 1999·12 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →