Inventor · disambiguated record
Eric M. Rentschler
Also filed as: RENTSCHLER ERIC · RENTSCHLER ERIC M · RENTSCHLER ERIC MCCUTCHEON
35 granted patents·3 pending applications·1,175 citations·filing 1995–2014
98Inventor score
Files withHEWLETT PACKARD DEVELOPMENT CO14HEWLETT PACKARD CO8NIXON SCOTT P5ADVANCED MICRO DEVICES INC3RENTSCHLER ERIC M3
Top patents by PatentIndex Score
38 records- 0197US7099994B2RAID memory systemHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Aug 29, 2006·242 cites·17 claims
- 0295US6678811B2Memory controller with 1X/MX write capabilityHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Jan 13, 2004·119 cites·6 claims
- 0393US6930932B2Data signal reception latch control using clock aligned relative to strobe signalHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Aug 16, 2005·70 cites·26 claims
- 0493US6625702B2Memory controller with support for memory modules comprised of non-homogeneous data width RAM devicesHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Sep 23, 2003·107 cites·33 claims
- 0590US8683265B2Debug state machine cross triggeringRENTSCHLER ERIC M·Filed 2010·Granted Mar 25, 2014·11 cites·19 claims
- 0690US5920326ACaching and coherency control of multiple geometry accelerators in a computer graphics systemHEWLETT PACKARD CO·Filed 1997·Granted Jul 6, 1999·145 cites·20 claims
- 0789US8566645B2Debug state machine and processor including the sameRENTSCHLER ERIC·Filed 2010·Granted Oct 22, 2013·24 cites·20 claims
- 0884US9037911B2Debug state machines and methods of their operationRENTSCHLER ERIC M·Filed 2011·Granted May 19, 2015·12 cites·19 claims
- 0984US5969726ACaching and coherency control of multiple geometry accelerators in a computer graphics systemHEWLETT PACKARD CO·Filed 1997·Granted Oct 19, 1999·86 cites·39 claims
- 1083US5940086ASystem and method for dynamically allocating data among geometry accelerators in a computer graphics systemHEWLETT PACKARD CO·Filed 1997·Granted Aug 17, 1999·84 cites·34 claims
- 1183US5821950AComputer graphics system utilizing parallel processing for enhanced performanceHEWLETT PACKARD CO·Filed 1996·Granted Oct 13, 1998·90 cites·14 claims
- 1277US7103793B2Memory controller having receiver circuitry capable of alternately generating one or more data streams as data is received at a data pad, in response to counts of strobe edges received at a strobe padHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Sep 5, 2006·18 cites·15 claims
- 1375US7103790B2Memory controller driver circuitry having a multiplexing stage to provide data to at least N-1 of N data propagation circuits, and having output merging circuitry to alternately couple the N data propagation circuits to a data pad to generate either a 1x or Mx stream of dataHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Sep 5, 2006·18 cites·14 claims
- 1473US6633965B2Memory controller with 1×/M× read capabilityFiled 2001·Granted Oct 14, 2003·15 cites·27 claims
- 1572US6889335B2Memory controller receiver circuitry with tri-state noise immunityHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted May 3, 2005·17 cites·42 claims
- 1671US6990562B2Memory controller to communicate with memory devices that are associated with differing data/strobe ratiosHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Jan 24, 2006·13 cites·20 claims
- 1770US8832500B2Multiple clock domain tracingNIXON SCOTT P·Filed 2012·Granted Sep 9, 2014·3 cites·24 claims
- 1870US7533285B2Synchronizing link delay measurement over serial linksHEWLETT PACKARD DEVELOPMENT CO·Filed 2004·Granted May 12, 2009·8 cites·26 claims
- 1968US8935574B2Correlating traces in a computing systemBEDWELL RYAN D·Filed 2011·Granted Jan 13, 2015·4 cites·20 claims
- 2067US7103826B2Memory system and controller for sameHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Sep 5, 2006·12 cites·16 claims
- 2165US9442815B2Distributed on-chip debug triggering with allocated bus linesNIXON SCOTT P·Filed 2012·Granted Sep 13, 2016·2 cites·15 claims
- 2261US9262293B2Debug apparatus and methods for dynamically switching power domainsADVANCED MICRO DEVICES INC·Filed 2013·Granted Feb 16, 2016·1 cites·18 claims
- 2357US6360301B1Coherency protocol for computer cacheHEWLETT PACKARD CO·Filed 1999·Granted Mar 19, 2002·30 cites·5 claims
- 2456US7289587B2Repeatability over communication linksHEWLETT PACKARD DEVELOPMENT CO·Filed 2004·Granted Oct 30, 2007·6 cites·30 claims
- 2553US9686536B2Method and apparatus for aggregation and streaming of monitoring dataADVANCED MICRO DEVICES INC·Filed 2014·Granted Jun 20, 2017·0 cites·18 claims
- 2652US7506130B2Mirrored computer memory on split busHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Mar 17, 2009·2 cites·3 claims
- 2747US9329963B2Debug apparatus and methods for dynamically switching power domainsADVANCED MICRO DEVICES INC·Filed 2013·Granted May 3, 2016·0 cites·18 claims
- 2847US6788135B1Terminating pathway for a clock signalHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Sep 7, 2004·4 cites·25 claims
- 2945US8959398B2Multiple clock domain debug capabilityNIXON SCOTT P·Filed 2012·Granted Feb 17, 2015·0 cites·20 claims
- 3044US7426596B2Integrated circuit with a scalable high-bandwidth architectureHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Sep 16, 2008·0 cites·19 claims
- 3144US5671373AData bus protocol for computer graphics systemHEWLETT PACKARD CO·Filed 1995·Granted Sep 23, 1997·11 cites·18 claims
- 3242US8595563B2Method and circuitry for debugging a power-gated circuitTSIEN BENJAMIN·Filed 2011·Granted Nov 26, 2013·0 cites·20 claims
- 3342US2003221058A1Mirrored computer memory on single busFiled 2002·Application pending·0 cites
- 3440US6381663B1Mechanism for implementing bus locking with a mixed architectureHEWLETT PACKARD CO·Filed 1999·Granted Apr 30, 2002·12 cites·20 claims
- 3539US9129061B2Method and apparatus for on-chip debuggingNIXON SCOTT P·Filed 2012·Granted Sep 8, 2015·0 cites·22 claims
- 3638US2014053036A1Debugging multiple exclusive sequences using dsm context switchesNIXON SCOTT P·Filed 2012·Application pending·0 cites
- 3737US5793660ACircuit for finding m modulo nHEWLETT PACKARD CO·Filed 1997·Granted Aug 11, 1998·9 cites·2 claims
- 3836US2012150474A1Debug state machine cross triggeringRENTSCHLER ERIC M·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →