Inventor · disambiguated record
Elio Colabella
Also filed as: COLABELLA ELIO
9 granted patents·38 citations·filing 1997–2000
85Inventor score
Top patents by PatentIndex Score
9 records- 0155US6380582B2Autoaligned etching process for realizing word lines in memory devices integrated semiconductor substratesST MICROELECTRONICS SRL·Filed 2000·Granted Apr 30, 2002·5 cites·7 claims
- 0254US6252274B1Process for making crosspoint memory devices with cells having a source channel which is autoaligned to the bit line and to the field oxideST MICROELECTRONICS SRL·Filed 2000·Granted Jun 26, 2001·5 cites·10 claims
- 0350US6630739B1Planarization structure and method for dielectric layersST MICROELECTRONICS SRL·Filed 2000·Granted Oct 7, 2003·3 cites·16 claims
- 0444US5994231AProcess for depositing a stratified dielectric structure for enhancing the planarity of semiconductor electronic devicesSGS THOMSON MICROELECTRONICS·Filed 1997·Granted Nov 30, 1999·12 cites·8 claims
- 0539US6156637AMethod of planarizing a semiconductor device by depositing a dielectric ply structureST MICROELECTRONICS SRL·Filed 1997·Granted Dec 5, 2000·7 cites·29 claims
- 0639US6057192AProcess for making crosspoint memory devices with cells having a source channel which is autoaligned to the bit line and to the field oxideST MICROELECTRONICS SRL·Filed 1998·Granted May 2, 2000·5 cites·9 claims
- 0729US6376306B1Method for forming non volatile memory structures on a semiconductor substrateST MICROELECTRONICS SRL·Filed 1999·Granted Apr 23, 2002·0 cites·11 claims
- 0828US6130165AAutoaligned etching process for realizing word lines in memory devices integrated semiconductor substratesST MICROELECTRONICS SRL·Filed 1997·Granted Oct 10, 2000·1 cites·8 claims
- 0927US6239037B1Autoaligned etching process for realizing word lines and improving the reliability of semiconductor integrated memory devicesST MICROELECTRONICS SRL·Filed 1999·Granted May 29, 2001·0 cites·8 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →