Inventor · disambiguated record
Claudio Brambilla
Also filed as: BRAMBILLA CLAUDIO
12 granted patents·88 citations·filing 1997–2004
90Inventor score
Top patents by PatentIndex Score
12 records- 0184US6825523B2Process for manufacturing a dual charge storage location memory cellST MICROELECTRONICS SRL·Filed 2002·Granted Nov 30, 2004·34 cites·27 claims
- 0256US6365456B1Process for manufacturing semiconductor integrated memory devices with cells matrix having virtual groundST MICROELECTRONICS SRL·Filed 2000·Granted Apr 2, 2002·6 cites·16 claims
- 0350US6063663AMethod for manufacturing a native MOS P-channel transistor with a process for manufacturing non-volatile memoriesSGS THOMSON MICROELECTRONICS·Filed 1998·Granted May 16, 2000·12 cites·7 claims
- 0449US6350671B1Method for autoaligning overlapped lines of a conductive material in integrated electronic circuitsST MICROELECTRONICS SRL·Filed 2000·Granted Feb 26, 2002·4 cites·11 claims
- 0549US6300195B1Process for manufacturing semiconductor integrated memory devices with cells matrix having virtual groundST MICROELECTRONICS SRL·Filed 2000·Granted Oct 9, 2001·5 cites·15 claims
- 0645US7115472B2Process for manufacturing a dual charge storage location memory cellST MICROELECTRONICS SRL·Filed 2004·Granted Oct 3, 2006·2 cites·20 claims
- 0740US6326266B1Method of manufacturing an EPROM memory device having memory cells organized in a tablecloth matrixST MICROELECTRONICS SRL·Filed 1998·Granted Dec 4, 2001·7 cites·10 claims
- 0838US5976933AProcess for manufacturing an integrated circuit comprising an array of memory cellsSGS THOMSON MICROELECTRONICS·Filed 1997·Granted Nov 2, 1999·8 cites·29 claims
- 0937US6251736B1Method for forming contactless MOS transistors and resulting devices, especially for use in non-volatile memory arraysST MICROELECTRONICS SRL·Filed 1999·Granted Jun 26, 2001·7 cites·15 claims
- 1030US5894065AMethod for improving the intermediate dielectric profile, particularly for non-volatile memoriesSGS THOMSON MICROELECTRONICS·Filed 1997·Granted Apr 13, 1999·2 cites·5 claims
- 1129US6353243B1Process for manufacturing an integrated circuit comprising an array of memory cellsSGS THOMSON MICROELECTRONICS·Filed 1999·Granted Mar 5, 2002·1 cites·4 claims
- 1227US6104058AMethod for improving the intermediate dielectric profile, particularly for non-volatile memoriesSGS THOMSON MICROELECTRONICS·Filed 1997·Granted Aug 15, 2000·0 cites·40 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →