Inventor · disambiguated record
Sin S. Tan
Also filed as: TAN SIN · TAN SIN S · TAN SIN SIM
21 granted patents·4 pending applications·200 citations·filing 1998–2024
95Inventor score
Files withINTEL CORP13SK HYNIX NAND PRODUCT SOLUTIONS CORP3TAN SIN S3RADHAKRISHNAN SIVAKUMAR2LOOI LILY PAO1
Top patents by PatentIndex Score
25 records- 0194US8607129B2Efficient and scalable cyclic redundancy check circuit using Galois-field arithmeticRADHAKRISHNAN SIVAKUMAR·Filed 2011·Granted Dec 10, 2013·20 cites·13 claims
- 0292US9417821B2Presentation of direct accessed storage under a logical drive modelSLAIGHT THOMAS M·Filed 2011·Granted Aug 16, 2016·19 cites·20 claims
- 0388US8275560B2Power measurement techniques of a system-on-chip (SOC)RADHAKRISHNAN SIVAKUMAR·Filed 2009·Granted Sep 25, 2012·17 cites·24 claims
- 0486US8782456B2Dynamic and idle power reduction sequence using recombinant clock and power gatingTAN SIN S·Filed 2010·Granted Jul 15, 2014·10 cites·30 claims
- 0582US2024378160A1Presentation of direct accessed storage under a logical drive modelSK HYNIX NAND PRODUCT SOLUTIONS CORP·Filed 2024·Application pending·0 cites
- 0681US11604746B2Presentation of direct accessed storage under a logical drive modelSK HYNIX NAND PRODUCT SOLUTIONS CORP·Filed 2020·Granted Mar 14, 2023·1 cites·17 claims
- 0778US12079149B2Presentation of direct accessed storage under a logical drive modelSK HYNIX NAND PRODUCT SOLUTIONS CORP·Filed 2023·Granted Sep 3, 2024·0 cites·21 claims
- 0878US9141469B2Efficient and scalable cyclic redundancy check circuit using Galois-field arithmeticINTEL CORP·Filed 2013·Granted Sep 22, 2015·5 cites·21 claims
- 0977US6298420B1Coherent variable length reads from system memoryINTEL CORP·Filed 2000·Granted Oct 2, 2001·23 cites·2 claims
- 1076US8850250B2Integration of processor and input/output hubLOOI LILY PAO·Filed 2010·Granted Sep 30, 2014·6 cites·20 claims
- 1169US8812878B2Limiting false wakeups of computing device components coupled via linksTAN SIN S·Filed 2009·Granted Aug 19, 2014·5 cites·20 claims
- 1267US8352764B2Dynamic squelch detection power controlINTEL CORP·Filed 2008·Granted Jan 8, 2013·4 cites·17 claims
- 1367US7065596B2Method and apparatus to resolve instruction starvationINTEL CORP·Filed 2002·Granted Jun 20, 2006·18 cites·37 claims
- 1465US6826619B1Method and apparatus for preventing starvation in a multi-node architectureINTEL CORP·Filed 2000·Granted Nov 30, 2004·11 cites·21 claims
- 1557US2016335208A1Presentation of direct accessed storage under a logical drive modelINTEL CORP·Filed 2016·Application pending·0 cites
- 1656US6622215B2Mechanism for handling conflicts in a multi-node computer architectureINTEL CORP·Filed 2000·Granted Sep 16, 2003·4 cites·15 claims
- 1752US6832268B2Mechanism to guarantee forward progress for incoming coherent input/output (I/O) transactions for caching I/O agent on address conflict with processor transactionsINTEL CORP·Filed 2002·Granted Dec 14, 2004·4 cites·22 claims
- 1846US5996038AIndividually resettable bus expander bridge mechanismINTEL CORP·Filed 1998·Granted Nov 30, 1999·18 cites·21 claims
- 1945US6061764ACoherent variable length reads which implicates multiple cache lines by a memory controller connected to a serial and a pipelined bus utilizing a plurality of atomic transactionsINTEL CORP·Filed 1998·Granted May 9, 2000·16 cites·12 claims
- 2044US7500029B2Maximal length packetsINTEL CORP·Filed 2004·Granted Mar 3, 2009·0 cites·26 claims
- 2144US6134632AController that supports data merging utilizing a slice addressable memory arrayINTEL CORP·Filed 1998·Granted Oct 17, 2000·19 cites·24 claims
- 2243US7386643B2Mechanism to guarantee forward progress for incoming coherent input/output (I/O) transactions for caching I/O agent on address conflict with processor transactionsTAN SIN S·Filed 2004·Granted Jun 10, 2008·0 cites·20 claims
- 2342US2008235461A1Technique and apparatus for combining partial write transactionsTAN SIN·Filed 2007·Application pending·0 cites
- 2440US9935653B2Enhanced cyclical redundancy check circuit based on galois-field arithmeticINTEL CORP·Filed 2015·Granted Apr 3, 2018·0 cites·25 claims
- 2538US2002087766A1Method and apparatus to implement a locked-bus transactionFiled 2000·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →