Inventor · disambiguated record
Frederic J. Neuveux
Also filed as: NEUVEUX FREDERIC · NEUVEUX FREDERIC J · NEUVEUX FREDERIC JEAN
15 granted patents·147 citations·filing 2004–2023
93Inventor score
Top patents by PatentIndex Score
15 records- 0196US7900105B2Dynamically reconfigurable shared scan-in test architectureSYNOPSYS INC·Filed 2010·Granted Mar 1, 2011·15 cites·35 claims
- 0296US7823034B2Pipeline of additional storage elements to shift input/output data of combinational scan compression circuitSYNOPSYS INC·Filed 2007·Granted Oct 26, 2010·41 cites·15 claims
- 0390US8645780B2Fully X-tolerant, very high scan compression scan test systems and techniquesSYNOPSYS INC·Filed 2013·Granted Feb 4, 2014·6 cites·7 claims
- 0490US7418640B2Dynamically reconfigurable shared scan-in test architectureSYNOPSYS INC·Filed 2004·Granted Aug 26, 2008·28 cites·7 claims
- 0588US7979763B2Fully X-tolerant, very high scan compression scan test systems and techniquesSYNOPSYS INC·Filed 2009·Granted Jul 12, 2011·12 cites·20 claims
- 0686US7774663B2Dynamically reconfigurable shared scan-in test architectureSYNOPSYS INC·Filed 2009·Granted Aug 10, 2010·8 cites·7 claims
- 0785US7596733B2Dynamically reconfigurable shared scan-in test architectureSYNOPSYS INC·Filed 2008·Granted Sep 29, 2009·8 cites·7 claims
- 0884US7836367B2Dynamically reconfigurable shared scan-in test architectureSYNOPSYS INC·Filed 2009·Granted Nov 16, 2010·7 cites·56 claims
- 0979US8464115B2Fully X-tolerant, very high scan compression scan test systems and techniquesWOHL PETER·Filed 2011·Granted Jun 11, 2013·3 cites·9 claims
- 1079US7958472B2Increasing scan compression by using X-chainsSYNOPSYS INC·Filed 2008·Granted Jun 7, 2011·10 cites·16 claims
- 1178US9157961B2Two-level compression through selective reseedingSYNOPSYS INC·Filed 2013·Granted Oct 13, 2015·4 cites·26 claims
- 1271US7836368B2Dynamically reconfigurable shared scan-in test architectureSYNOPSYS INC·Filed 2009·Granted Nov 16, 2010·3 cites·28 claims
- 1365US7743299B2Dynamically reconfigurable shared scan-in test architectureSYNOPSYS INC·Filed 2008·Granted Jun 22, 2010·2 cites·5 claims
- 1458US12352811B1Validating test patterns ported between different levels of a hierarchical design of an integrated circuitSYNOPSYS INC·Filed 2023·Granted Jul 8, 2025·0 cites·20 claims
- 1556US11132484B1Controlling clocks and resets in a logic built in self-testSYNOPSYS INC·Filed 2020·Granted Sep 28, 2021·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →