Inventor · disambiguated record
Margaret Simmons-Matthews
Also filed as: SIMMONS-MATTHEWS MARGARET · SIMMONS-MATTHEWS MARGARET R · SIMMONS-MATTHEWS MARGARET ROSE
14 granted patents·8 pending applications·174 citations·filing 2002–2014
93Inventor score
Files withTEXAS INSTRUMENTS INC8SIMMONS-MATTHEWS MARGARET R3WACHTLER KURT2WEST JEFFREY ALAN2ABBOTT DONALD C1
Top patents by PatentIndex Score
22 records- 0194US8097964B2IC having TSV arrays with reduced TSV induced stressWEST JEFFREY ALAN·Filed 2009·Granted Jan 17, 2012·39 cites·17 claims
- 0293US8344749B2Through carrier dual side loop-back testing of TSV die after die attach to substrateTEXAS INSTRUMENTS INC·Filed 2010·Granted Jan 1, 2013·23 cites·22 claims
- 0393US8313982B2Stacked die assemblies including TSV dieDUNNE RAJIV·Filed 2010·Granted Nov 20, 2012·24 cites·17 claims
- 0491US8526186B2Electronic assembly including die on substrate with heat spreader having an open window on the dieYOKOYA SATOSHI·Filed 2011·Granted Sep 3, 2013·17 cites·20 claims
- 0590US8344493B2Warpage control features on the bottomside of TSV die lateral to protruding bottomside tipsTEXAS INSTRUMENTS INC·Filed 2011·Granted Jan 1, 2013·14 cites·11 claims
- 0689US8575758B2Laser-assisted cleaving of a reconstituted wafer for stacked die assembliesWEST JEFFREY ALAN·Filed 2011·Granted Nov 5, 2013·10 cites·9 claims
- 0786US8227295B2IC die having TSV and wafer level underfill and stacked IC devices comprising a workpiece solder connected to the TSVSIMMONS-MATTHEWS MARGARET R·Filed 2009·Granted Jul 24, 2012·17 cites·11 claims
- 0880US8759154B2TCE compensation for package substrates for reduced die warpage assemblyTEXAS INSTRUMENTS INC·Filed 2012·Granted Jun 24, 2014·4 cites·9 claims
- 0978US8471577B2Lateral coupling enabled topside only dual-side testing of TSV die attached to package substrateSTILLMAN DANIEL JOSEPH·Filed 2010·Granted Jun 25, 2013·8 cites·23 claims
- 1074US8298863B2TCE compensation for package substrates for reduced die warpage assemblySIMMONS-MATTHEWS MARGARET·Filed 2010·Granted Oct 30, 2012·4 cites·7 claims
- 1169US8288849B2Method for attaching wide bus memory and serial memory to a processor within a chip scale package footprintWACHTLER KURT·Filed 2010·Granted Oct 16, 2012·3 cites·12 claims
- 1262US8815642B2Laser-assisted cleaving of a reconstituted wafer for stacked die assembliesTEXAS INSTRUMENTS INC·Filed 2013·Granted Aug 26, 2014·1 cites·11 claims
- 1359US6768212B2Semiconductor packages and methods for manufacturing such semiconductor packagesTEXAS INSTRUMENTS INC·Filed 2003·Granted Jul 27, 2004·10 cites·10 claims
- 1453US2014183719A1Electronic assembly includes a composite carrierTEXAS INSTRUMENTS INC·Filed 2014·Application pending·0 cites
- 1546US8597978B2Method for attaching wide bus memory and serial memory to a processor within a chip scale package footprintWACHTLER KURT·Filed 2012·Granted Dec 3, 2013·0 cites·5 claims
- 1645US2013099384A1Stacked IC Devices Comprising a Workpiece Solder Connected to the TSVSIMMONS-MATTHEWS MARGARET R·Filed 2012·Application pending·0 cites
- 1741US2014151895A1Die having through-substrate vias with deformation protected tipsTEXAS INSTRUMENTS INC·Filed 2012·Application pending·0 cites
- 1841US2014124900A1Through-silicon via (tsv) die and method to control warpageTEXAS INSTRUMENTS INC·Filed 2012·Application pending·0 cites
- 1939US2013082407A1Integrated Circuit Package And MethodABBOTT DONALD C·Filed 2011·Application pending·0 cites
- 2039US2005266661A1Semiconductor wafer with ditched scribe streetLI LEI·Filed 2004·Application pending·0 cites
- 2133US2003090558A1Package for printhead chipFiled 2002·Application pending·0 cites
- 2233US2010190294A1Methods for controlling wafer and package warpage during assembly of very thin dieSIMMONS-MATTHEWS MARGARET R·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →