Inventor · disambiguated record
Keith H. Tabakman
Also filed as: TABAKMAN KEITH · TABAKMAN KEITH H · TABAKMAN KEITH HOWARD
35 granted patents·4 pending applications·105 citations·filing 2006–2020
96Inventor score
Top patents by PatentIndex Score
39 records- 0196US9812400B1Contact line having insulating spacer therein and method of forming sameGLOBALFOUNDRIES INC·Filed 2016·Granted Nov 7, 2017·19 cites·15 claims
- 0294US8492234B2Field effect transistor deviceCHAN KEVIN K·Filed 2010·Granted Jul 23, 2013·16 cites·12 claims
- 0392US8361859B2Stressed transistor with improved metastabilityIBM·Filed 2010·Granted Jan 29, 2013·13 cites·15 claims
- 0491US10635007B1Apparatus and method for aligning integrated circuit layers using multiple grating materialsGLOBALFOUNDRIES INC·Filed 2018·Granted Apr 28, 2020·11 cites·16 claims
- 0589US9613855B1Methods of forming MIS contact structures on transistor devices in CMOS applicationsGLOBALFOUNDRIES INC·Filed 2016·Granted Apr 4, 2017·7 cites·32 claims
- 0687US10825811B2Gate cut first isolation formation with contact forming process mask protectionGLOBALFOUNDRIES INC·Filed 2019·Granted Nov 3, 2020·4 cites·18 claims
- 0785US9536900B2Forming fins of different semiconductor materials on the same substrateGLOBALFOUNDRIES INC·Filed 2014·Granted Jan 3, 2017·7 cites·13 claims
- 0883US10580875B2Middle of line structuresGLOBALFOUNDRIES INC·Filed 2018·Granted Mar 3, 2020·3 cites·20 claims
- 0983US10243077B2FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growthIBM·Filed 2017·Granted Mar 26, 2019·2 cites·10 claims
- 1081US10734233B2FinFET with high-k spacer and self-aligned contact capping layerGLOBALFOUNDRIES INC·Filed 2018·Granted Aug 4, 2020·3 cites·14 claims
- 1180US9917190B2FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growthIBM·Filed 2015·Granted Mar 13, 2018·2 cites·7 claims
- 1280US9312364B2finFET with dielectric isolation after gate module for improved source and drain region epitaxial growthIBM·Filed 2014·Granted Apr 12, 2016·3 cites·11 claims
- 1379US8815656B2Semiconductor device and method with greater epitaxial growth on 110 crystal planeIBM·Filed 2012·Granted Aug 26, 2014·4 cites·22 claims
- 1478US8618617B2Field effect transistor deviceIBM·Filed 2013·Granted Dec 31, 2013·3 cites·9 claims
- 1577US10991796B2Source/drain contact depth controlGLOBALFOUNDRIES US INC·Filed 2018·Granted Apr 27, 2021·2 cites·10 claims
- 1672US10262996B2Third type of metal gate stack for CMOS devicesIBM·Filed 2017·Granted Apr 16, 2019·1 cites·14 claims
- 1772US9059286B2Pre-gate, source/drain strain layer formationIBM·Filed 2014·Granted Jun 16, 2015·2 cites·11 claims
- 1867US11081583B2FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growthIBM·Filed 2019·Granted Aug 3, 2021·0 cites·10 claims
- 1965US10978566B2Middle of line structuresGLOBALFOUNDRIES US INC·Filed 2020·Granted Apr 13, 2021·0 cites·18 claims
- 2061US10741554B2Third type of metal gate stack for CMOS devicesIBM·Filed 2019·Granted Aug 11, 2020·0 cites·19 claims
- 2158US9006052B2Self aligned device with enhanced stress and methods of manufactureHOLT JUDSON R·Filed 2010·Granted Apr 14, 2015·1 cites·19 claims
- 2257US10615279B2FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growthIBM·Filed 2016·Granted Apr 7, 2020·0 cites·11 claims
- 2357US8426265B2Method for growing strain-inducing materials in CMOS circuits in a gate first flowBAI BO·Filed 2010·Granted Apr 23, 2013·1 cites·16 claims
- 2457US7895008B2Method of performing measurement sampling of lots in a manufacturing processIBM·Filed 2008·Granted Feb 22, 2011·1 cites·22 claims
- 2555US9634006B2Third type of metal gate stack for CMOS devicesIBM·Filed 2014·Granted Apr 25, 2017·0 cites·13 claims
- 2653US10049985B2Contact line having insulating spacer therein and method of forming sameGLOBALFOUNDRIES INC·Filed 2017·Granted Aug 14, 2018·0 cites·14 claims
- 2751US10192791B1Semiconductor devices with robust low-k sidewall spacers and method for producing the sameGLOBALFOUNDRIES INC·Filed 2018·Granted Jan 29, 2019·0 cites·20 claims
- 2850US8779525B2Method for growing strain-inducing materials in CMOS circuits in a gate first flowIBM·Filed 2013·Granted Jul 15, 2014·0 cites·19 claims
- 2948US9171800B2Electrical fuse with bottom contactsIBM·Filed 2014·Granted Oct 27, 2015·0 cites·16 claims
- 3048US2013134444A1Stressed transistor with improved metastabilityIBM·Filed 2013·Application pending·0 cites
- 3147US10297504B2Methods of forming a gate structure-to-source/drain conductive contact and the resulting devicesGLOBALFOUNDRIES INC·Filed 2017·Granted May 21, 2019·0 cites·19 claims
- 3246US2011215376A1Pre-gate, source/drain strain layer formationIBM·Filed 2010·Application pending·0 cites
- 3345US2012181578A1Pre-gate, source/drain strain layer formationHOLT JUDSON R·Filed 2012·Application pending·0 cites
- 3443US9293593B2Self aligned device with enhanced stress and methods of manufactureHOLT JUDSON R·Filed 2012·Granted Mar 22, 2016·0 cites·13 claims
- 3539US7781239B2Semiconductor device defect type determination method and structureIBM·Filed 2008·Granted Aug 24, 2010·0 cites·11 claims
- 3638US7751920B2Method and system of data weighted object orientation for data miningIBM·Filed 2006·Granted Jul 6, 2010·0 cites·17 claims
- 3738US2019131424A1Methods for forming ic structure having recessed gate spacers and related ic structuresGLOBALFOUNDRIES INC·Filed 2017·Application pending·0 cites
- 3837US9831123B2Methods of forming MIS contact structures on transistor devicesGLOBALFOUNDRIES INC·Filed 2016·Granted Nov 28, 2017·0 cites·26 claims
- 3937US8084788B2Method of forming source and drain of a field-effect-transistor and structure thereofHOLT JUDSON ROBERT·Filed 2008·Granted Dec 27, 2011·0 cites·13 claims
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