Inventor · disambiguated record
Yung-Hsuan Yang
Also filed as: YANG YUNG-HSUAN
7 granted patents·1 pending application·79 citations·filing 2020–2024
86Inventor score
Files withATOMERA INC8
Top patents by PatentIndex Score
8 records- 0198US11869968B2Semiconductor device including a superlattice and an asymmetric channel and related methodsATOMERA INC·Filed 2022·Granted Jan 9, 2024·8 cites·17 claims
- 0298US11329154B2Semiconductor device including a superlattice and an asymmetric channel and related methodsATOMERA INC·Filed 2020·Granted May 10, 2022·14 cites·18 claims
- 0398US11094818B2Method for making a semiconductor device including a superlattice and an asymmetric channel and related methodsATOMERA INC·Filed 2020·Granted Aug 17, 2021·18 cites·23 claims
- 0498US11075078B1Method for making a semiconductor device including a superlattice within a recessed etchATOMERA INC·Filed 2020·Granted Jul 27, 2021·21 cites·24 claims
- 0597US11569368B2Method for making semiconductor device including a superlattice and providing reduced gate leakageATOMERA INC·Filed 2020·Granted Jan 31, 2023·8 cites·18 claims
- 0697US11469302B2Semiconductor device including a superlattice and providing reduced gate leakageATOMERA INC·Filed 2020·Granted Oct 11, 2022·10 cites·14 claims
- 0787US2025107139A1Semiconductor device including a superlattice and an asymmetric channel and related methodsATOMERA INC·Filed 2024·Application pending·0 cites
- 0885US12199180B2Semiconductor device including a superlattice and an asymmetric channel and related methodsATOMERA INC·Filed 2023·Granted Jan 14, 2025·0 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →