Inventor · disambiguated record
Yoshio Takamine
Also filed as: TAKAMINE YOSHIO
9 granted patents·1 pending application·246 citations·filing 1986–2008
90Inventor score
Top patents by PatentIndex Score
10 records- 0186US4899273ACircuit simulation method with clock event suppression for debugging LSI circuitsHITACHI LTD·Filed 1986·Granted Feb 6, 1990·53 cites·2 claims
- 0280US7366965B2Semiconductor integrated circuitRENESAS TECH CORP·Filed 2004·Granted Apr 29, 2008·25 cites·9 claims
- 0373US6536031B2Method for generating behavior model description of circuit and apparatus for logic verificationHITACHI LTD·Filed 2001·Granted Mar 18, 2003·19 cites·18 claims
- 0472US5245550AApparatus for wire routing of VLSIHITACHI LTD·Filed 1992·Granted Sep 14, 1993·64 cites·6 claims
- 0566US4833619AAutomatic logic design systemHITACHI LTD·Filed 1986·Granted May 23, 1989·37 cites·8 claims
- 0654US4933839AVector processorHITACHI LTD·Filed 1987·Granted Jun 12, 1990·21 cites·8 claims
- 0743US5051941AMethod and apparatus for logical simulationHITACHI LTD·Filed 1990·Granted Sep 24, 1991·15 cites·14 claims
- 0840US2009063913A1Semiconductor integrated circuitRENESAS TECH CORP·Filed 2008·Application pending·0 cites
- 0936US4811213AVector processor with vector registersHITACHI LTD·Filed 1986·Granted Mar 7, 1989·7 cites·7 claims
- 1030US5592655ALogic simulation methodHITACHI LTD·Filed 1994·Granted Jan 7, 1997·5 cites·14 claims
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