Inventor · disambiguated record
Mark Dechene
Also filed as: DECHENE MARK · DECHENE MARK J · DECHENE MARK JOSEPH
8 granted patents·6 pending applications·2 citations·filing 2011–2022
73Inventor score
Top patents by PatentIndex Score
14 records- 0167US10761844B2Systems and methods to predict load data valuesINTEL CORP·Filed 2018·Granted Sep 1, 2020·1 cites·25 claims
- 0264US10860319B2Apparatus and method for an early page predictor for a memory paging subsystemINTEL CORP·Filed 2018·Granted Dec 8, 2020·1 cites·29 claims
- 0351US10956160B2Method and apparatus for a multi-level reservation station with instruction recirculationINTEL CORP·Filed 2019·Granted Mar 23, 2021·0 cites·33 claims
- 0448US9495159B2Two level re-order bufferINTEL CORP·Filed 2013·Granted Nov 15, 2016·0 cites·30 claims
- 0547US2024111679A1Hardware processor having multiple memory prefetchers and multiple prefetch filtersINTEL CORP·Filed 2022·Application pending·0 cites
- 0646US2024037036A1Scheduling merged store operations in compliance with store ordering rulesINTEL CORP·Filed 2022·Application pending·0 cites
- 0743US10379864B2Processor prefetch throttling based on short streamsINTEL CORP·Filed 2016·Granted Aug 13, 2019·0 cites·15 claims
- 0843US10228956B2Supporting binary translation alias detection in an out-of-order processorINTEL CORP·Filed 2016·Granted Mar 12, 2019·0 cites·20 claims
- 0943US2024143502A1Apparatus and method for a zero level cache/memory architectureINTEL CORP·Filed 2022·Application pending·0 cites
- 1042US10853078B2Method and apparatus for supporting speculative memory optimizationsINTEL CORP·Filed 2018·Granted Dec 1, 2020·0 cites·20 claims
- 1141US2020310798A1Technology For Providing Memory Atomicity With Low OverheadSHEVGOOR MANJUNATH·Filed 2019·Application pending·0 cites
- 1240US9652236B2Instruction and logic for non-blocking register reclamationSRINIVASAN SRIKANTH T·Filed 2013·Granted May 16, 2017·0 cites·15 claims
- 1340US2020210193A1Hardware profiler to track instruction sequence information including a blacklisting mechanism and a whitelisting mechanismINTEL CORP·Filed 2018·Application pending·0 cites
- 1440US2014156977A1Enabling and disabling a second jump execution unit for branch mispredictionDECHENE MARK J·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →