Inventor · disambiguated record
Zeshan A. Chishti
Also filed as: CHISHTI ZESHAN · CHISHTI ZESHAN A
33 granted patents·9 pending applications·266 citations·filing 2008–2023
96Inventor score
Top patents by PatentIndex Score
42 records- 0196US9418723B2Techniques to reduce memory cell refreshes for a memory deviceINTEL CORP·Filed 2014·Granted Aug 16, 2016·46 cites·25 claims
- 0295US9001608B1Coordinating power mode switching and refresh operations in a memory deviceCHISHTI ZESHAN A·Filed 2013·Granted Apr 7, 2015·55 cites·25 claims
- 0394US9703708B2System and method for thread scheduling on reconfigurable processor coresINTEL CORP·Filed 2013·Granted Jul 11, 2017·25 cites·18 claims
- 0494US8640005B2Method and apparatus for using cache memory in a system that supports a low power stateWILKERSON CHRISTOPHER B·Filed 2010·Granted Jan 28, 2014·39 cites·22 claims
- 0592US9921972B2Method and apparatus for implementing a heterogeneous memory subsystemINTEL CORP·Filed 2016·Granted Mar 20, 2018·8 cites·19 claims
- 0691US9472248B2Method and apparatus for implementing a heterogeneous memory subsystemINTEL CORP·Filed 2014·Granted Oct 18, 2016·14 cites·22 claims
- 0790US10496544B2Aggregated write back in a direct mapped two level memoryINTEL CORP·Filed 2016·Granted Dec 3, 2019·7 cites·22 claims
- 0890US9583182B1Multi-level memory managementINTEL CORP·Filed 2016·Granted Feb 28, 2017·9 cites·21 claims
- 0987US10102134B2Instruction and logic for run-time evaluation of multiple prefetchersINTEL CORP·Filed 2016·Granted Oct 16, 2018·5 cites·20 claims
- 1085US8276142B2Hardware support for thread scheduling on multi-core processorsALAMELDEEN ALAA R·Filed 2009·Granted Sep 25, 2012·16 cites·23 claims
- 1184US9417879B2Systems and methods for managing reconfigurable processor coresINTEL CORP·Filed 2013·Granted Aug 16, 2016·6 cites·19 claims
- 1284US9183144B2Power gating a portion of a cache memoryINTEL CORP·Filed 2012·Granted Nov 10, 2015·7 cites·17 claims
- 1381US9176875B2Power gating a portion of a cache memoryINTEL CORP·Filed 2013·Granted Nov 3, 2015·5 cites·17 claims
- 1477US9378021B2Instruction and logic for run-time evaluation of multiple prefetchersCHISHTI ZESHAN A·Filed 2014·Granted Jun 28, 2016·4 cites·20 claims
- 1576US8151012B2Virtual row buffers for use with random access memoryKIM CHANGKYU·Filed 2009·Granted Apr 3, 2012·10 cites·16 claims
- 1670US9792212B2Virtual shared cache mechanism in a processing deviceINTEL CORP·Filed 2014·Granted Oct 17, 2017·2 cites·20 claims
- 1767US8245111B2Performing multi-bit error correction on a cache lineCHISHTI ZESHAN A·Filed 2008·Granted Aug 14, 2012·6 cites·23 claims
- 1862US11513957B2Processor and method implementing a cacheline demote machine instructionINTEL CORP·Filed 2020·Granted Nov 29, 2022·0 cites·20 claims
- 1960US8806285B2Dynamically allocatable memory error mitigationALAMELDEEN ALAA R·Filed 2012·Granted Aug 12, 2014·1 cites·30 claims
- 2060US8484418B2Methods and apparatuses for idle-prioritized memory ranksCHISHTI ZESHAN A·Filed 2010·Granted Jul 9, 2013·1 cites·16 claims
- 2157US12316735B2Technologies for memory and I/O efficient operations on homomorphically encrypted dataINTEL CORP·Filed 2020·Granted May 27, 2025·0 cites·11 claims
- 2257US10817425B2Hardware/software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloadsINTEL CORP·Filed 2014·Granted Oct 27, 2020·0 cites·12 claims
- 2353US2025004781A1Method and apparatus to implement adaptive branch prediction throttlingINTEL CORP·Filed 2023·Application pending·0 cites
- 2451US2025004775A1Auto-predication for loops with dynamically varying interation countsINTEL CORP·Filed 2023·Application pending·0 cites
- 2550US10621094B2Coarse tag replacementINTEL CORP·Filed 2017·Granted Apr 14, 2020·0 cites·16 claims
- 2650US9286224B2Constraining prefetch requests to a processor socketINTEL CORP·Filed 2013·Granted Mar 15, 2016·0 cites·22 claims
- 2749US2020133884A1Nvram system memory with memory side cache that favors written to items and/or includes regions with customized temperature induced speed settingsINTEL CORP·Filed 2019·Application pending·0 cites
- 2848US10241916B2Sparse superline removalINTEL CORP·Filed 2017·Granted Mar 26, 2019·0 cites·21 claims
- 2948US10120806B2Multi-level system memory with near memory scrubbing based on predicted far memory idle timeINTEL CORP·Filed 2016·Granted Nov 6, 2018·0 cites·18 claims
- 3046US10108549B2Method and apparatus for pre-fetching data in a system having a multi-level system memoryINTEL CORP·Filed 2015·Granted Oct 23, 2018·0 cites·17 claims
- 3146US9921961B2Multi-level memory managementINTEL CORP·Filed 2017·Granted Mar 20, 2018·0 cites·18 claims
- 3245US10417135B2Near memory miss prediction to reduce memory access latencyINTEL CORP·Filed 2017·Granted Sep 17, 2019·0 cites·22 claims
- 3344US10860244B2Method and apparatus for multi-level memory early page demotionINTEL CORP·Filed 2017·Granted Dec 8, 2020·0 cites·15 claims
- 3444US10452312B2Apparatus, system, and method to determine a demarcation voltage to use to read a non-volatile memoryINTEL CORP·Filed 2016·Granted Oct 22, 2019·0 cites·25 claims
- 3543US9710380B2Managing shared cache by multi-core processorINTEL CORP·Filed 2013·Granted Jul 18, 2017·0 cites·20 claims
- 3643US2020226124A1Edge batch reordering for streaming graph analyticsINTEL CORP·Filed 2020·Application pending·0 cites
- 3742US2019102314A1Tag cache adaptive power gatingINTEL CORP·Filed 2017·Application pending·0 cites
- 3841US10261901B2Method and apparatus for unneeded block prediction in a computing system having a last level cache and a multi-level system memoryINTEL CORP·Filed 2015·Granted Apr 16, 2019·0 cites·17 claims
- 3941US2018188797A1Link power management scheme based on link's prior historyINTEL CORP·Filed 2016·Application pending·0 cites
- 4041US2018285274A1Apparatus, method and system for just-in-time cache associativityINTEL CORP·Filed 2017·Application pending·0 cites
- 4140US2020226066A1Apparatus and method for efficient management of multi-level memoryINTEL CORP·Filed 2020·Application pending·0 cites
- 4232US2017046074A1Adaptive Data Compression for Data Storage in a Memory DeviceINTEL CORP·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →