Inventor · disambiguated record
Ramesh Sathianathan
Also filed as: SATHIANATHAN RAMESH
9 granted patents·162 citations·filing 2002–2016
88Inventor score
Technology areasG06F
Top patents by PatentIndex Score
9 records- 0193US6848088B1Measure of analysis performed in property checkingMENTOR GRAPHICS CORP·Filed 2002·Granted Jan 25, 2005·69 cites·10 claims
- 0286US7890897B2Measure of analysis performed in property checkingMENTOR GRAPHICS CORP·Filed 2007·Granted Feb 15, 2011·11 cites·23 claims
- 0385US8418121B2Measure of analysis performed in property checkingLEVITT JEREMY RUTLEDGE·Filed 2011·Granted Apr 9, 2013·7 cites·21 claims
- 0485US7454324B1Selection of initial states for formal verificationSEAWRIGHT JAMES ANDREW GARRARD·Filed 2003·Granted Nov 18, 2008·57 cites·18 claims
- 0575US7318205B2Measure of analysis performed in property checkingLEVITT JEREMY RUTLEDGE·Filed 2004·Granted Jan 8, 2008·15 cites·26 claims
- 0668US9262557B2Measure of analysis performed in property checkingMENTOR GRAPHICS CORP·Filed 2013·Granted Feb 16, 2016·1 cites·5 claims
- 0757US9684760B2Measure of analysis performed in property checkingMENTOR GRAPHICS CORP·Filed 2016·Granted Jun 20, 2017·0 cites·18 claims
- 0857US8819599B2Hierarchical verification of clock domain crossingsKWOK KA-KEI·Filed 2009·Granted Aug 26, 2014·2 cites·19 claims
- 0952US9117044B2Hierarchical verification of clock domain crossingsMENTOR GRAPHICS CORP·Filed 2014·Granted Aug 25, 2015·0 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →