Inventor · disambiguated record
Prashant Sethia
Also filed as: SETHIA PRASHANT
11 granted patents·218 citations·filing 2013–2022
91Inventor score
Top patents by PatentIndex Score
11 records- 0196US8788995B1System and method for guiding remedial transformations of a circuit design defined by physical implementation data to reduce needed physical corrections for detected timing violations in the circuit designCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Jul 22, 2014·55 cites·16 claims
- 0294US10776547B1Infinite-depth path-based analysis of operational timing for circuit designCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Sep 15, 2020·20 cites·20 claims
- 0394US8863052B1System and method for generating and using a structurally aware timing model for representative operation of a circuit designCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Oct 14, 2014·44 cites·18 claims
- 0492US9875333B1Comprehensive path based analysis processCADENCE DESIGN SYSEMS INC·Filed 2016·Granted Jan 23, 2018·51 cites·20 claims
- 0592US9589096B1Method and apparatus for integrating spice-based timing using sign-off path-based analysisCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Mar 7, 2017·12 cites·20 claims
- 0688US10289774B1Systems and methods for reuse of delay calculation in static timing analysisCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted May 14, 2019·9 cites·20 claims
- 0788US10114920B1Method and apparatus for performing sign-off timing analysis of circuit designs using inter-power domain logicCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Oct 30, 2018·8 cites·20 claims
- 0887US9633159B1Method and system for performing distributed timing signoff and optimizationCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Apr 25, 2017·7 cites·30 claims
- 0985US9529962B1System and method for generating and using sibling nets model for shared delay calculation across multi-instantiated blocks in the circuit designCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Dec 27, 2016·6 cites·20 claims
- 1085US9405882B1High performance static timing analysis system and method for input/output interfacesCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Aug 2, 2016·6 cites·19 claims
- 1157US12423504B1Adaptive path based analysis processCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Sep 23, 2025·0 cites·13 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →