Inventor · disambiguated record
David Wolpert
Also filed as: WOLPERT DAVID · WOLPERT DAVID S · WOLPERT DAVID SOLOMON
45 granted patents·40 pending applications·80 citations·filing 2008–2024
96Inventor score
Files withIBM85
Top patents by PatentIndex Score
85 records- 0191US7525373B1Compensation of process and voltage variability in multi-threshold dynamic voltage scaling circuitsIBM·Filed 2008·Granted Apr 28, 2009·26 cites·1 claims
- 0290US12057387B2Decoupling capacitor inside gate cut trenchIBM·Filed 2020·Granted Aug 6, 2024·2 cites·21 claims
- 0390US11308257B1Stacked via rivets in chip hotspotsIBM·Filed 2020·Granted Apr 19, 2022·2 cites·17 claims
- 0485US10885260B1Fin-based fill cell optimizationIBM·Filed 2019·Granted Jan 5, 2021·4 cites·20 claims
- 0585US10248749B2Automated attribute propagation and hierarchical consistency checking for non-standard extensionsIBM·Filed 2018·Granted Apr 2, 2019·3 cites·20 claims
- 0685US10223487B2Automated attribute propagation and hierarchical consistency checking for non-standard extensionsIBM·Filed 2017·Granted Mar 5, 2019·3 cites·7 claims
- 0785US9977851B2Automated attribute propagation and hierarchical consistency checking for non-standard extensionsIBM·Filed 2017·Granted May 22, 2018·3 cites·17 claims
- 0881US7898285B2Optimal local supply voltage determination circuitIBM·Filed 2008·Granted Mar 1, 2011·10 cites·20 claims
- 0980US11906570B2Processor frequency improvement based on antenna optimizationIBM·Filed 2023·Granted Feb 20, 2024·0 cites·15 claims
- 1080US11586798B1Avoiding electrostatic discharge events from cross-hierarchy tie netsIBM·Filed 2021·Granted Feb 21, 2023·1 cites·18 claims
- 1179US9971861B2Selective boundary overlay insertion for hierarchical circuit designIBM·Filed 2016·Granted May 15, 2018·3 cites·14 claims
- 1278US10699050B2Front-end-of-line shape merging cell placement and optimizationIBM·Filed 2018·Granted Jun 30, 2020·2 cites·19 claims
- 1374US7508250B1Testing for normal or reverse temperature related delay variations in integrated circuitsIBM·Filed 2008·Granted Mar 24, 2009·7 cites·1 claims
- 1472US9892222B1Automated attribute propagation and hierarchical consistency checking for non-standard extensionsIBM·Filed 2016·Granted Feb 13, 2018·1 cites·10 claims
- 1571US10896283B1Noise-based optimization for integrated circuit designIBM·Filed 2019·Granted Jan 19, 2021·2 cites·20 claims
- 1671US9384857B2Error control using threshold based comparison of error signaturesIBM·Filed 2014·Granted Jul 5, 2016·2 cites·15 claims
- 1771US9041428B2Placement of storage cells on an integrated circuitIBM·Filed 2013·Granted May 26, 2015·3 cites·19 claims
- 1869US12500144B2Backside self aligned skip viaIBM·Filed 2023·Granted Dec 16, 2025·0 cites·20 claims
- 1969US2025301785A1Cross-couple connect in stacked field effect transistor semiconductorsIBM·Filed 2024·Application pending·0 cites
- 2068US11754615B2Processor frequency improvement based on antenna optimizationIBM·Filed 2021·Granted Sep 12, 2023·0 cites·20 claims
- 2166US9043683B2Error protection for integrated circuitsIBM·Filed 2013·Granted May 26, 2015·3 cites·15 claims
- 2264US12266393B2Negative capacitance for ferroelectric capacitive memory cellIBM·Filed 2022·Granted Apr 1, 2025·0 cites·20 claims
- 2364US9626220B2Computer system using partially functional processor coreIBM·Filed 2015·Granted Apr 18, 2017·1 cites·14 claims
- 2463US12382621B2Decoupling capacitor inside gate cut trenchIBM·Filed 2022·Granted Aug 5, 2025·0 cites·19 claims
- 2562US2025285964A1Deep via structures for stacked transistor devicesIBM·Filed 2024·Application pending·0 cites
- 2662US2025318248A1Deep via structures for stacked transistor devicesIBM·Filed 2024·Application pending·0 cites
- 2762US2025280601A1Stacked fet with stacked power railIBM·Filed 2024·Application pending·0 cites
- 2862US2025357342A1Subtractive power lines with wrap-around power planeIBM·Filed 2024·Application pending·0 cites
- 2962US2025379145A1Stacked fet with backside replacement metal gateIBM·Filed 2024·Application pending·0 cites
- 3061US11055465B2Fill techniques for avoiding Boolean DRC failures during cell placementIBM·Filed 2019·Granted Jul 6, 2021·0 cites·20 claims
- 3161US10831980B2Using unused wires on very-large-scale integration chips for power supply decouplingIBM·Filed 2019·Granted Nov 10, 2020·0 cites·20 claims
- 3261US2025273568A1Mixed pitch levels for back-end-of-line wiring layersIBM·Filed 2024·Application pending·0 cites
- 3361US2025218863A1Orthogonal metal lines at the same metal levelIBM·Filed 2023·Application pending·0 cites
- 3461US2025374666A1Flexible arrangement of semiconductor devicesIBM·Filed 2024·Application pending·0 cites
- 3561US2025266344A1Back end of the line wiring between device layersIBM·Filed 2024·Application pending·0 cites
- 3661US2024201583A1Physically detectable id introduced by lithography sraf insertion for heterogeneous integrationIBM·Filed 2022·Application pending·0 cites
- 3760US2025185291A1Embedded jumper connectionIBM·Filed 2023·Application pending·0 cites
- 3860US2025253238A1Backside to frontside connection between different metal tracksIBM·Filed 2024·Application pending·0 cites
- 3960US2025293145A1Interconnect structure with intra-level metal line connectorsIBM·Filed 2024·Application pending·0 cites
- 4060US2025380503A1Self-aligned backside cutIBM·Filed 2024·Application pending·0 cites
- 4160US2025140650A1Via connection in middle beol wiringIBM·Filed 2023·Application pending·0 cites
- 4260US2025194199A1Pitch configuration for back-end-of-line wiringIBM·Filed 2023·Application pending·0 cites
- 4360US2025194197A1Gate tie-down to backside power railIBM·Filed 2023·Application pending·0 cites
- 4459US12271674B2Generating a power delivery network based on the routing of signal wires within a circuit designIBM·Filed 2022·Granted Apr 8, 2025·0 cites·17 claims
- 4559US11916384B2Region-based power grid generation through modification of an initial power grid based on timing analysisIBM·Filed 2021·Granted Feb 27, 2024·0 cites·20 claims
- 4659US2025301674A1Trench capacitor in backside diffusion breakIBM·Filed 2024·Application pending·0 cites
- 4759US2025194182A1Stacked device structures with varying layer characteristicsIBM·Filed 2023·Application pending·0 cites
- 4859US2025204048A1Self-aligned backside channel removalIBM·Filed 2023·Application pending·0 cites
- 4959US2025226313A1Interconnect lines with line width profileIBM·Filed 2024·Application pending·0 cites
- 5059US2025054863A1Flexible trackplan for power deliveryIBM·Filed 2023·Application pending·0 cites
Showing the top 50 of 85 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →