Inventor · disambiguated record
Josep M. Codina
Also filed as: CODINA JOSEP M
12 granted patents·6 pending applications·71 citations·filing 2006–2018
89Inventor score
Technology areasG06F
Top patents by PatentIndex Score
18 records- 0184US7895415B2Cache sharing based thread controlINTEL CORP·Filed 2007·Granted Feb 22, 2011·16 cites·6 claims
- 0283US8612698B2Replacement policy for hot code detectionLOPEZ PEDRO·Filed 2008·Granted Dec 17, 2013·16 cites·18 claims
- 0377US8909902B2Systems, methods, and apparatuses to decompose a sequential program into multiple threads, execute said threads, and reconstruct the sequential executionLATORRE FERNANDO·Filed 2009·Granted Dec 9, 2014·10 cites·13 claims
- 0476US8261046B2Access of register files of other threads using synchronizationGIBERT ENRIC·Filed 2006·Granted Sep 4, 2012·12 cites·22 claims
- 0568US9940138B2Utilization of register checkpointing mechanism with pointer swapping to resolve multithreading mis-speculationsLOPEZ PEDRO·Filed 2009·Granted Apr 10, 2018·5 cites·20 claims
- 0666US9811341B2Managed instruction cache prefetchingSTAVROU KYRIAKOS A·Filed 2011·Granted Nov 7, 2017·4 cites·5 claims
- 0766US8190652B2Achieving coherence between dynamically optimized code and original codeLATORRE FERNANDO·Filed 2007·Granted May 29, 2012·4 cites·10 claims
- 0862US10621092B2Merging level cache and data cache units having indicator bits related to speculative executionINTEL CORP·Filed 2014·Granted Apr 14, 2020·1 cites·20 claims
- 0959US10013326B2Propagating a prefetching profile bit from a prefetch queue to a data cache to indicate that a line was prefetched in response to an instruction within a code regionMARTINEZ RAUL·Filed 2011·Granted Jul 3, 2018·1 cites·18 claims
- 1058US9983880B2Method and apparatus for improved thread selectionINTEL CORP·Filed 2014·Granted May 29, 2018·1 cites·16 claims
- 1153US8898646B2Method and apparatus for flexible, accurate, and/or efficient code profilingCODINA ENRIC GIBERT·Filed 2010·Granted Nov 25, 2014·1 cites·16 claims
- 1252US2019004916A1Profiling asynchronous events resulting from the execution of software at code region granularityINTEL CORP·Filed 2018·Application pending·0 cites
- 1342US10157063B2Instruction and logic for optimization level aware branch predictionINTEL CORP·Filed 2012·Granted Dec 18, 2018·0 cites·6 claims
- 1440US2016011874A1Silent memory instructions and miss-rate tracking to optimize switching policy on threads in a processing deviceORENSTEIN DORON·Filed 2014·Application pending·0 cites
- 1538US2013268735A1Support for speculative ownership without dataGIBERT CODINA ENRIC·Filed 2011·Application pending·0 cites
- 1637US2014156976A1Method, apparatus and system for selective execution of a commit instructionGIBERT CODINA ENRIC·Filed 2011·Application pending·0 cites
- 1737US2014281434A1Path profiling using hardware and software combinationMADRILES CARLOS·Filed 2013·Application pending·0 cites
- 1832US2013326199A1Method and apparatus for controlling a mxcsrMAGKLIS GRIGORIOS·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →