Inventor · disambiguated record
Eitan Joshua
Also filed as: JOSHUA EITAN
20 granted patents·2 pending applications·82 citations·filing 2004–2024
93Inventor score
Files withMARVELL WORLD TRADE LTD7MARVELL ISRAEL MISL LTD4MARVELL SEMICONDUCTOR ISRAEL3HABANA LABS LTD2STOLER GIL2
Top patents by PatentIndex Score
22 records- 0192US10268395B1Systems and methods for communicating addressable requests to a programmable input/output memory over a hardware bridgeMARVELL INT LTD·Filed 2017·Granted Apr 23, 2019·13 cites·20 claims
- 0292US7206988B1Error-correction memory architecture for testing production errorsMARVELL SEMICONDUCTOR ISRAEL·Filed 2005·Granted Apr 17, 2007·23 cites·1 claims
- 0387US12475054B1Dynamic cache allocation in artificial intelligence acceleratorHABANA LABS LTD·Filed 2024·Granted Nov 18, 2025·1 cites·20 claims
- 0486US10769098B2Methods and systems for accessing host memory through non-volatile memory over fabric bridging with direct target accessMARVELL WORLD TRADE LTD·Filed 2017·Granted Sep 8, 2020·5 cites·20 claims
- 0579US8089378B1Synchronous multi-clock protocol converterSTOLER GIL·Filed 2010·Granted Jan 3, 2012·8 cites·17 claims
- 0677US9317433B1Multi-core processing system having cache coherency in dormant modeMARVELL ISRAEL MISL LTD·Filed 2014·Granted Apr 19, 2016·6 cites·18 claims
- 0775US6988237B1Error-correction memory architecture for testing production errorsMARVELL SEMICONDUCTOR ISRAEL·Filed 2004·Granted Jan 17, 2006·16 cites·24 claims
- 0874US12066936B1Cache memory with decoupled control pathsHABANA LABS LTD·Filed 2022·Granted Aug 20, 2024·1 cites·25 claims
- 0971US8756362B1Methods and systems for determining a cache addressJOSHUA EITAN·Filed 2011·Granted Jun 17, 2014·4 cites·20 claims
- 1062US7478308B1Error-correction memory architecture for testing productionMARVELL ISRAEL MISL LTD·Filed 2007·Granted Jan 13, 2009·3 cites·25 claims
- 1160US8924652B2Simultaneous eviction and cleaning operations in a cacheHABUSHA ADI·Filed 2012·Granted Dec 30, 2014·1 cites·20 claims
- 1258US11397703B2Methods and systems for accessing host memory through non-volatile memory over fabric bridging with direct target accessMARVELL ASIA PTE LTD·Filed 2020·Granted Jul 26, 2022·0 cites·20 claims
- 1356US9298627B2Shared op-symmetric update-sensitive variablesMARVELL WORLD TRADE LTD·Filed 2014·Granted Mar 29, 2016·0 cites·20 claims
- 1455US10230542B2Interconnected ring network in a multi-processor systemMARVELL WORLD TRADE LTD·Filed 2017·Granted Mar 12, 2019·0 cites·15 claims
- 1555US9454480B2Interconnected ring network in a multi-processor systemMARVELL WORLD TRADE LTD·Filed 2014·Granted Sep 27, 2016·0 cites·20 claims
- 1654US9521011B2Interconnected ring network in a multi-processor systemMARVELL WORLD TRADE LTD·Filed 2014·Granted Dec 13, 2016·0 cites·17 claims
- 1754US9298628B2Shared op-symmetric update-sensitive variablesMARVELL WORLD TRADE LTD·Filed 2014·Granted Mar 29, 2016·0 cites·8 claims
- 1852US2014201326A1Interconnected ring network in a multi-processor systemMARVELL WORLD TRADE LTD·Filed 2014·Application pending·0 cites
- 1951US7984358B1Error-correction memory architecture for testing production errorsMARVELL ISRAEL MISL LTD·Filed 2009·Granted Jul 19, 2011·1 cites·20 claims
- 2041US9892083B1Method and apparatus for controlling a rate of transmitting data units to a processing coreMARVELL ISRAEL MISL LTD·Filed 2015·Granted Feb 13, 2018·0 cites·20 claims
- 2139US8760324B1Synchronous multi-clock protocol converterSTOLER GIL·Filed 2011·Granted Jun 24, 2014·0 cites·19 claims
- 2236US2008195901A1Op-code based built-in-self-testMARVELL SEMICONDUCTOR ISRAEL·Filed 2008·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →