Inventor · disambiguated record
Valeria Bertacco
Also filed as: BERTACCO VALERIA · BERTACCO VALERIA MARIA
13 granted patents·2 pending applications·57 citations·filing 1999–2021
89Inventor score
Top patents by PatentIndex Score
15 records- 0187US8341473B2Microprocessor and method for detecting faults thereinBERTACCO VALERIA·Filed 2011·Granted Dec 25, 2012·12 cites·1 claims
- 0283US11748521B2Privacy-enhanced computation via sequestered encryptionAGITA LABS INC·Filed 2021·Granted Sep 5, 2023·2 cites·56 claims
- 0383US11748490B2Computer system with moving target defenses against vulnerability attacksUNIV MICHIGAN·Filed 2021·Granted Sep 5, 2023·1 cites·19 claims
- 0482US11232212B2Computer system with moving target defenses against vulnerability attacksUNIV MICHIGAN REGENTS·Filed 2019·Granted Jan 25, 2022·3 cites·19 claims
- 0578US8738349B2Gate-level logic simulator using multiple processor architecturesBERTACCO VALERIA·Filed 2010·Granted May 27, 2014·8 cites·39 claims
- 0677US8365110B2Automatic error diagnosis and correction for RTL designsUNIV MICHIGAN·Filed 2008·Granted Jan 29, 2013·10 cites·33 claims
- 0773US7966538B2Microprocessor and method for detecting faults thereinUNIV MICHIGAN·Filed 2008·Granted Jun 21, 2011·5 cites·11 claims
- 0869US8051368B2Microprocessor and method for detecting faults thereinUNIVERISTY OF MICHIGAN·Filed 2011·Granted Nov 1, 2011·2 cites·8 claims
- 0958US12105855B2Privacy-enhanced computation via sequestered encryptionAGITA LABS INC·Filed 2021·Granted Oct 1, 2024·0 cites·20 claims
- 1051US9411007B2System and method for statistical post-silicon validationUNIV MICHIGAN REGENTS·Filed 2012·Granted Aug 9, 2016·1 cites·20 claims
- 1147US9645882B2Field repairable logicBERTACCO VALERIA·Filed 2008·Granted May 9, 2017·0 cites·9 claims
- 1241US6493841B1Method and apparatus for determining expected values during circuit design verificationSYNOPSYS INC·Filed 1999·Granted Dec 10, 2002·13 cites·15 claims
- 1341US2022277072A1Thwarting control plane attacks with displaced and dilated address spacesUNIV MICHIGAN·Filed 2020·Application pending·0 cites
- 1439US11868283B2Hybrid on/off-chip memory architecture for graph analyticsUNIV MICHIGAN REGENTS·Filed 2020·Granted Jan 9, 2024·0 cites·15 claims
- 1536US2011087861A1System for High-Efficiency Post-Silicon Verification of a ProcessorUNIV MICHIGAN·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →