Inventor · disambiguated record
Barry Joe Wolford
Also filed as: WOLFORD BARRY · WOLFORD BARRY J · WOLFORD BARRY JOE
40 granted patents·3 pending applications·550 citations·filing 1994–2012
98Inventor score
Files withIBM33QUALCOMM INC7GANASAN JAYA PRAKASH SUBRAMANIAM1HOFMANN RICHARD GERARD1WOLFORD BARRY JOE1
Top patents by PatentIndex Score
43 records- 0192US7590021B2System and method to reduce dynamic RAM power consumption via the use of valid data indicatorsQUALCOMM INC·Filed 2007·Granted Sep 15, 2009·27 cites·30 claims
- 0292US6504790B1Configurable DDR write-channel phase advance and delay capabilityIBM·Filed 2001·Granted Jan 7, 2003·71 cites·14 claims
- 0392US6424198B1Memory clock generation with configurable phase advance and delay capabilityIBM·Filed 2001·Granted Jul 23, 2002·75 cites·22 claims
- 0491US7984202B2Device directed memory barriersQUALCOMM INC·Filed 2007·Granted Jul 19, 2011·25 cites·31 claims
- 0590US8077019B2Method of associating groups of classified source addresses with vibration patternsHOFMANN RICHARD GERARD·Filed 2006·Granted Dec 13, 2011·21 cites·20 claims
- 0683US6826656B2Reducing power in a snooping cache based multiprocessor environmentIBM·Filed 2002·Granted Nov 30, 2004·35 cites·27 claims
- 0781US7620783B2Method and apparatus for obtaining memory status information cross-reference to related applicationsQUALCOMM INC·Filed 2006·Granted Nov 17, 2009·13 cites·37 claims
- 0881US6493285B1Method and apparatus for sampling double data rate memory read dataIBM·Filed 2001·Granted Dec 10, 2002·31 cites·10 claims
- 0976US6823411B2N-way psuedo cross-bar having an arbitration feature using discrete processor local bussesIBM·Filed 2002·Granted Nov 23, 2004·22 cites·23 claims
- 1076US6452865B1Method and apparatus for supporting N-bit width DDR memory interface using a common symmetrical read data path with 2N-bit internal bus widthIBM·Filed 2001·Granted Sep 17, 2002·23 cites·17 claims
- 1173US7783817B2Method and apparatus for conditional broadcast of barrier operationsQUALCOMM INC·Filed 2006·Granted Aug 24, 2010·6 cites·17 claims
- 1273US7093058B2Single request data transfer regardless of size and alignmentIBM·Filed 2005·Granted Aug 15, 2006·6 cites·4 claims
- 1373US6834378B2System on a chip bus with automatic pipeline stage insertion for timing closureIBM·Filed 2002·Granted Dec 21, 2004·15 cites·11 claims
- 1472US7593279B2Concurrent status register readQUALCOMM INC·Filed 2006·Granted Sep 22, 2009·8 cites·38 claims
- 1570US7035958B2Re-ordering a first request within a FIFO request queue to a different queue position when the first request receives a retry response from the targetIBM·Filed 2002·Granted Apr 25, 2006·15 cites·21 claims
- 1670US5535226AOn-chip ECC statusIBM·Filed 1994·Granted Jul 9, 1996·54 cites·18 claims
- 1768US6970962B2Transfer request pipeline throttlingIBM·Filed 2003·Granted Nov 29, 2005·13 cites·19 claims
- 1867US7127562B2Ensuring orderly forward progress in granting snoop castout requestsIBM·Filed 2003·Granted Oct 24, 2006·12 cites·12 claims
- 1965US6907502B2Method for moving snoop pushes to the front of a request queueIBM·Filed 2002·Granted Jun 14, 2005·10 cites·27 claims
- 2063US7328312B2Method and bus prefetching mechanism for implementing enhanced buffer controlIBM·Filed 2005·Granted Feb 5, 2008·2 cites·3 claims
- 2162US6976132B2Reducing latency of a snoop tenureIBM·Filed 2003·Granted Dec 13, 2005·8 cites·20 claims
- 2262US6973520B2System and method for providing improved bus utilization via target directed completionIBM·Filed 2002·Granted Dec 6, 2005·8 cites·23 claims
- 2358US7210030B2Programmable memory initialization system and methodIBM·Filed 2004·Granted Apr 24, 2007·6 cites·21 claims
- 2457US7089376B2Reducing snoop response time for snoopers without copies of requested data via snoop filteringIBM·Filed 2003·Granted Aug 8, 2006·8 cites·13 claims
- 2554US7707347B2Data path master/slave data processing device apparatusIBM·Filed 2009·Granted Apr 27, 2010·0 cites·16 claims
- 2654US7526595B2Data path master/slave data processing device apparatus and methodIBM·Filed 2002·Granted Apr 28, 2009·3 cites·4 claims
- 2754US6985972B2Dynamic cache coherency snooper presence with variable snoop latencyIBM·Filed 2002·Granted Jan 10, 2006·3 cites·20 claims
- 2853US7685373B2Selective snooping by snoop masters to locate updated dataIBM·Filed 2008·Granted Mar 23, 2010·0 cites·9 claims
- 2953US7490201B2Method and bus prefetching mechanism for implementing enhanced buffer controlIBM·Filed 2007·Granted Feb 10, 2009·0 cites·7 claims
- 3051US7296175B2System on a chip bus with automatic pipeline stage insertion for timing closureIBM·Filed 2004·Granted Nov 13, 2007·1 cites·9 claims
- 3151US7174410B2Method, apparatus and computer program product for write data transferIBM·Filed 2003·Granted Feb 6, 2007·2 cites·20 claims
- 3249US2011055495A1Memory Controller Page Management Devices, Systems, and MethodsQUALCOMM INC·Filed 2009·Application pending·0 cites
- 3348US6993619B2Single request data transfer regardless of size and alignmentIBM·Filed 2003·Granted Jan 31, 2006·1 cites·12 claims
- 3448US2010169527A1Data path master/slave data processing deviceIBM·Filed 2010·Application pending·0 cites
- 3547US6807608B2Multiprocessor environment supporting variable-sized coherency transactionsIBM·Filed 2002·Granted Oct 19, 2004·2 cites·24 claims
- 3647US5664165AGeneration of a synthetic clock signal in synchronism with a high frequency clock signal and corresponding to a low frequency clock signalIBM·Filed 1995·Granted Sep 2, 1997·21 cites·16 claims
- 3746US7395380B2Selective snooping by snoop masters to locate updated dataIBM·Filed 2003·Granted Jul 1, 2008·0 cites·8 claims
- 3841US2013191572A1Transaction ordering to avoid bus deadlocksQUALCOMM INC·Filed 2012·Application pending·0 cites
- 3940US9262326B2Method and apparatus to enable the cooperative signaling of a shared bus interrupt in a multi-rank memory subsystemWOLFORD BARRY JOE·Filed 2006·Granted Feb 16, 2016·0 cites·36 claims
- 4040US6981166B2Method, apparatus, and computer program product for pacing clocked operationsIBM·Filed 2002·Granted Dec 27, 2005·0 cites·15 claims
- 4135US8861410B2Method and apparatus for scalable network transaction identifier for interconnectsGANASAN JAYA PRAKASH SUBRAMANIAM·Filed 2011·Granted Oct 14, 2014·0 cites·42 claims
- 4229US6266741B1Method and apparatus to reduce system bus latency on a cache miss with address acknowledgmentsIBM·Filed 1998·Granted Jul 24, 2001·3 cites·16 claims
- 4328US6134620ATri-state bus contention circuit preventing false switching caused by poor synchronizationIBM·Filed 1998·Granted Oct 17, 2000·0 cites·11 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →