Inventor · disambiguated record
Yin-Pin Wang
Also filed as: WANG YIN · WANG YIN-PIN · WANG YIN-PIN ERIC
21 granted patents·6 pending applications·236 citations·filing 2000–2025
94Inventor score
Files withTAIWAN SEMICONDUCTOR MFG CO LTD10TAIWAN SEMICONDUCTOR MFG9ERICSSON TELEFON AB L M2CHENG SHUI-MING1TAIWAIN SEMICONDUCTOR MFG COMP1
Top patents by PatentIndex Score
27 records- 0196US10468500B1FinFET fabrication methodsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Nov 5, 2019·9 cites·20 claims
- 0293US7750338B2Dual-SiGe epitaxy for MOS devicesTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Jul 6, 2010·27 cites·20 claims
- 0391US7449753B2Write margin improvement for SRAM cells with SiGe stressorsTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Nov 11, 2008·18 cites·19 claims
- 0489US6277709B1Method of forming shallow trench isolation structureVANGUARD INT SEMICONDUCT CORP·Filed 2000·Granted Aug 21, 2001·78 cites·12 claims
- 0588US10497577B2Fin field-effect transistor device and methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Dec 3, 2019·4 cites·20 claims
- 0686US6960512B2Method for manufacturing a semiconductor device having an improved disposable spacerTAIWAIN SEMICONDUCTOR MFG COMP·Filed 2003·Granted Nov 1, 2005·50 cites·21 claims
- 0784US2024371970A1Finfet fabrication methodsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 0881US7253062B2Semiconductor device with asymmetric pocket implantsTAIWAN SEMICONDUCTOR MFG·Filed 2005·Granted Aug 7, 2007·8 cites·5 claims
- 0980US11276766B2FinFET fabrication methodsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Mar 15, 2022·1 cites·20 claims
- 1080US6902980B2Method of fabricating a high performance MOSFET device featuring formation of an elevated source/drain regionTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Jun 7, 2005·24 cites·19 claims
- 1179US12068392B2FinFET fabrication methodsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Aug 20, 2024·0 cites·20 claims
- 1278US11271692B2Special subframe utilization for NB-IoT transmission in TDD modeERICSSON TELEFON AB L M·Filed 2018·Granted Mar 8, 2022·2 cites·7 claims
- 1376US2025301741A1Enlarged backside contactTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 1475US10964548B2Fin field-effect transistor device and methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Mar 30, 2021·1 cites·20 claims
- 1571US11735430B2Fin field-effect transistor device and methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Aug 22, 2023·0 cites·20 claims
- 1666US12349432B2Enlarged backside contactTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Jul 1, 2025·0 cites·20 claims
- 1760US6656845B2Method for forming semiconductor substrate with convex shaped active regionTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Dec 2, 2003·7 cites·18 claims
- 1853US8848675B2Time-division multiplexed pilot signal for integrated mobile broadcastsERICSSON TELEFON AB L M·Filed 2013·Granted Sep 30, 2014·0 cites·17 claims
- 1951US7453121B2Body contact formation in partially depleted silicon on insulator deviceTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Nov 18, 2008·4 cites·19 claims
- 2051US7009248B2Semiconductor device with asymmetric pocket implantsTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Mar 7, 2006·3 cites·6 claims
- 2144US10504898B2Fin field-effect transistor structure and method for forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Dec 10, 2019·0 cites·20 claims
- 2244US2005275022A1Depletion-merged FET design in bulk siliconCHENG SHUI-MING·Filed 2005·Application pending·0 cites
- 2340US7129547B2Method of fabricating a high performance MOSFET device featuring formation of an elevated source/drain regionTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Oct 31, 2006·0 cites·9 claims
- 2439US2005260776A1Structure and method for extraction of parasitic junction capacitance in deep submicron technologyTAIWAN SEMICONDUCTOR MFG·Filed 2004·Application pending·0 cites
- 2538US2005145881A1Depletion-merged FET design in bulk siliconFiled 2003·Application pending·0 cites
- 2638US2005186722A1Method and structure for CMOS device with stress relaxed by ion implantation of carbon or oxygen containing ionsFiled 2004·Application pending·0 cites
- 2736US9466716B2Dual-SiGe epitaxy for MOS devicesWANG YIN-PIN·Filed 2010·Granted Oct 11, 2016·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →