Inventor · disambiguated record
Randy M. Bonella
Also filed as: BONELLA RANDY · BONELLA RANDY M
34 granted patents·2 pending applications·4,753 citations·filing 1991–2010
98Inventor score
Top patents by PatentIndex Score
36 records- 0199US6742098B1Dual-port buffer-to-memory interfaceINTEL CORP·Filed 2000·Granted May 25, 2004·445 cites·20 claims
- 0299US6658509B1Multi-tier point-to-point ring memory interfaceINTEL CORP·Filed 2000·Granted Dec 2, 2003·373 cites·36 claims
- 0399US6487102B1Memory module having buffer for isolating stacked memory devicesINTEL CORP·Filed 2000·Granted Nov 26, 2002·286 cites·26 claims
- 0499US6477614B1Method for implementing multiple memory buses on a memory moduleINTEL CORP·Filed 2000·Granted Nov 5, 2002·308 cites·22 claims
- 0598US6625687B1Memory module employing a junction circuit for point-to-point connection isolation, voltage translation, data synchronization, and multiplexing/demultiplexingINTEL CORP·Filed 2000·Granted Sep 23, 2003·324 cites·12 claims
- 0698US6587912B2Method and apparatus for implementing multiple memory buses on a memory moduleINTEL CORP·Filed 1998·Granted Jul 1, 2003·407 cites·32 claims
- 0798US6553450B1Buffer to multiply memory interfaceINTEL CORP·Filed 2000·Granted Apr 22, 2003·310 cites·23 claims
- 0898US6493250B2Multi-tier point-to-point buffered memory interfaceINTEL CORP·Filed 2000·Granted Dec 10, 2002·223 cites·24 claims
- 0998US6369605B1Self-terminated driver to prevent signal reflections of transmissions between electronic devicesINTEL CORP·Filed 2000·Granted Apr 9, 2002·148 cites·29 claims
- 1098US6317352B1Apparatus for implementing a buffered daisy chain connection between a memory controller and memory modulesINTEL CORP·Filed 2000·Granted Nov 13, 2001·522 cites·10 claims
- 1197US7024518B2Dual-port buffer-to-memory interfaceINTEL CORP·Filed 2002·Granted Apr 4, 2006·151 cites·24 claims
- 1297US6747887B2Memory module having buffer for isolating stacked memory devicesINTEL CORP·Filed 2002·Granted Jun 8, 2004·128 cites·5 claims
- 1396US6820163B1Buffering data transfer between a chipset and memory modulesINTEL CORP·Filed 2000·Granted Nov 16, 2004·118 cites·21 claims
- 1496US6449213B1Memory interface having source-synchronous command/address signalingINTEL CORP·Filed 2000·Granted Sep 10, 2002·115 cites·23 claims
- 1595US6928571B1Digital system of adjusting delays on circuit boardsINTEL CORP·Filed 2000·Granted Aug 9, 2005·116 cites·35 claims
- 1695US6530006B1System and method for providing reliable transmission in a buffered memory systemINTEL CORP·Filed 2000·Granted Mar 4, 2003·112 cites·19 claims
- 1792US6697888B1Buffering and interleaving data transfer between a chipset and memory modulesINTEL CORP·Filed 2000·Granted Feb 24, 2004·75 cites·24 claims
- 1889US7941592B2Method and apparatus for high reliability data storage and retrieval operations in multi-level flash cellsBONELLA RANDY M·Filed 2008·Granted May 10, 2011·27 cites·15 claims
- 1988US6928593B1Memory module and memory component built-in self testINTEL CORP·Filed 2000·Granted Aug 9, 2005·46 cites·64 claims
- 2087US5537555AFully pipelined and highly concurrent memory controllerCOMPAQ COMPUTER CORP·Filed 1993·Granted Jul 16, 1996·128 cites·9 claims
- 2186US5325503ACache memory system which snoops an operation to a first location in a cache line and does not snoop further operations to locations in the same lineCOMPAQ COMPUTER CORP·Filed 1992·Granted Jun 28, 1994·107 cites·10 claims
- 2282US7681004B2Advanced dynamic disk memory moduleADDMM LLC·Filed 2006·Granted Mar 16, 2010·15 cites·20 claims
- 2378US5471590ABus master arbitration circuitry having improved prioritizationCOMPAQ COMPUTER CORP·Filed 1994·Granted Nov 28, 1995·78 cites·9 claims
- 2473US5446863ACache snoop latency prevention apparatusCOMPAQ COMPUTER CORP·Filed 1993·Granted Aug 29, 1995·53 cites·3 claims
- 2568US7249232B2Buffering and interleaving data transfer between a chipset and memory modulesINTEL CORP·Filed 2004·Granted Jul 24, 2007·11 cites·26 claims
- 2657US5333293AMultiple input frequency memory controllerCOMPAQ COMPUTER CORP·Filed 1991·Granted Jul 26, 1994·31 cites·9 claims
- 2756US5797020ABus master arbitration circuitry having improved prioritizationCOMPAQ COMPUTER CORP·Filed 1996·Granted Aug 18, 1998·31 cites·15 claims
- 2845US5625824ACircuit for selectively preventing a microprocessor from posting write cyclesCOMPAQ COMPUTER CORP·Filed 1995·Granted Apr 29, 1997·17 cites·18 claims
- 2944US6397291B2Method and apparatus for retrieving data from a data storage deviceINTEL CORP·Filed 2000·Granted May 28, 2002·0 cites·27 claims
- 3044US2010223422A1Advanced Dynamic Disk Memory ModuleBONELLA RANDY M·Filed 2010·Application pending·0 cites
- 3142US2007136523A1Advanced dynamic disk memory module special operationsBONELLA RANDY M·Filed 2006·Application pending·0 cites
- 3240US6192459B1Method and apparatus for retrieving data from a data storage deviceINTEL CORP·Filed 1998·Granted Feb 20, 2001·10 cites·5 claims
- 3339US5790869ACircuit for selectively preventing a microprocessor from posting write cyclesCOMPAQ COMPUTER CORP·Filed 1997·Granted Aug 4, 1998·11 cites·18 claims
- 3439US5404559AApparatus for asserting an end of cycle signal to a processor bus in a computer system if a special cycle is detected on the processor bus without taking action on the special cycleCOMPAQ COMPUTER CORP·Filed 1993·Granted Apr 4, 1995·10 cites·7 claims
- 3539US5253358ACache memory expansion and transparent interconnectionCOMPAQ COMPUTER CORP·Filed 1992·Granted Oct 12, 1993·15 cites·14 claims
- 3632US5818794AInternally controlled signal system for controlling the operation of a deviceINTEL CORP·Filed 1997·Granted Oct 6, 1998·2 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →