Inventor · disambiguated record
Jason Sheu
Also filed as: SHEU JASON
5 granted patents·7 citations·filing 2007–2012
71Inventor score
Technology areasG06F
Top patents by PatentIndex Score
5 records- 0171US8526257B2Processor with memory delayed bit line prechargingMARVELL WORLD TRADE LTD·Filed 2012·Granted Sep 3, 2013·2 cites·20 claims
- 0270US8295110B2Processor instruction cache with dual-read modesSUTARDJA SEHAT·Filed 2011·Granted Oct 23, 2012·2 cites·20 claims
- 0367US8027218B2Processor instruction cache with dual-read modesMARVELL WORLD TRADE LTD·Filed 2008·Granted Sep 27, 2011·3 cites·52 claims
- 0451US7787324B2Processor instruction cache with dual-read modesMARVELL WORLD TRADE LTD·Filed 2007·Granted Aug 31, 2010·0 cites·37 claims
- 0548US8089823B2Processor instruction cache with dual-read modesSUTARDJA SEHAT·Filed 2010·Granted Jan 3, 2012·0 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →