Inventor · disambiguated record
Satyendra Singh Chauhan
Also filed as: CHAUHAN SATYENDRA · CHAUHAN SATYENDRA S · CHAUHAN SATYENDRA SINGH
25 granted patents·510 citations·filing 2003–2021
96Inventor score
Top patents by PatentIndex Score
25 records- 0197US8017439B2Dual carrier for joining IC die or wafers to TSV wafersTEXAS INSTRUMENTS INC·Filed 2010·Granted Sep 13, 2011·26 cites·20 claims
- 0296US7057284B2Fine pitch low-cost flip chip substrateTEXAS INSTRUMENTS INC·Filed 2004·Granted Jun 6, 2006·92 cites·10 claims
- 0396US6888255B2Built-up bump pad structure and method for sameTEXAS INSTRUMENTS INC·Filed 2003·Granted May 3, 2005·144 cites·10 claims
- 0495US6849944B2Using a supporting structure to control collapse of a die towards a die pad during a reflow process for coupling the die to the die padTEXAS INSTRUMENTS INC·Filed 2003·Granted Feb 1, 2005·107 cites·37 claims
- 0592US7973416B2Thru silicon enabled die stacking schemeTEXAS INSTRUMENTS INC·Filed 2009·Granted Jul 5, 2011·26 cites·18 claims
- 0692US7915080B2Bonding IC die to TSV wafersTEXAS INSTRUMENTS INC·Filed 2009·Granted Mar 29, 2011·30 cites·16 claims
- 0790US8178976B2IC device having low resistance TSV comprising ground connectionDUNNE RAJIV·Filed 2009·Granted May 15, 2012·18 cites·14 claims
- 0889US11177197B2Semiconductor package with solder standoffTEXAS INSTRUMENTS INC·Filed 2019·Granted Nov 16, 2021·5 cites·24 claims
- 0983US8193093B2Thru silicon enabled die stacking schemeCHAUHAN SATYENDRA SINGH·Filed 2011·Granted Jun 5, 2012·9 cites·8 claims
- 1082US8154134B2Packaged electronic devices with face-up die having TSV connection to leads and die padBONIFIELD THOMAS D·Filed 2009·Granted Apr 10, 2012·15 cites·14 claims
- 1181US11658130B2Conductive plate stress reduction featureTEXAS INSTRUMENTS INC·Filed 2020·Granted May 23, 2023·1 cites·30 claims
- 1279US8431481B2IC device having low resistance TSV comprising ground connectionDUNNE RAJIV·Filed 2012·Granted Apr 30, 2013·4 cites·11 claims
- 1377US10892405B2Hall-effect sensor package with added current pathTEXAS INSTRUMENTS INC·Filed 2019·Granted Jan 12, 2021·2 cites·21 claims
- 1477US8053873B2IC having voltage regulated integrated Faraday shieldTEXAS INSTRUMENTS INC·Filed 2009·Granted Nov 8, 2011·7 cites·19 claims
- 1577US7635914B2Multi layer low cost cavity substrate fabrication for pop packagesTEXAS INSTRUMENTS INC·Filed 2007·Granted Dec 22, 2009·8 cites·13 claims
- 1676US7790597B2Solder cap application process on copper bump using solder powder filmTEXAS INSTRUMENTS INC·Filed 2008·Granted Sep 7, 2010·7 cites·11 claims
- 1773US10128219B2Multi-chip module including stacked power devices with metal clipTEXAS INSTRUMENTS INC·Filed 2013·Granted Nov 13, 2018·3 cites·13 claims
- 1870US11557722B2Hall-effect sensor package with added current pathTEXAS INSTRUMENTS INC·Filed 2021·Granted Jan 17, 2023·0 cites·20 claims
- 1969US11908780B2Semiconductor package with solder standoffTEXAS INSTRUMENTS INC·Filed 2021·Granted Feb 20, 2024·0 cites·24 claims
- 2066US11930590B2Stress relief for flip-chip packaged devicesTEXAS INSTRUMENTS INC·Filed 2021·Granted Mar 12, 2024·0 cites·12 claims
- 2166US8039309B2Systems and methods for post-circuitization assemblyTEXAS INSTRUMENTS INC·Filed 2008·Granted Oct 18, 2011·3 cites·20 claims
- 2266US7883936B2Multi layer low cost cavity substrate fabrication for PoP packagesTEXAS INSTRUMENTS INC·Filed 2009·Granted Feb 8, 2011·3 cites·7 claims
- 2354US11495580B2Multi-chip module including stacked power devices with metal clipTEXAS INSTRUMENTS INC·Filed 2018·Granted Nov 8, 2022·0 cites·20 claims
- 2452US8436475B2IC device having low resistance TSV comprising ground connectionDUNNE RAJIV·Filed 2012·Granted May 7, 2013·0 cites·10 claims
- 2552US7323405B2Fine pitch low cost flip chip substrateTEXAS INSTRUMENTS INC·Filed 2006·Granted Jan 29, 2008·0 cites·11 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →