Inventor · disambiguated record
Hsia Choo
Also filed as: CHOO HSIA LIANG
3 granted patents·1 pending application·54 citations·filing 2002–2005
71Inventor score
Files withCHARTERED SEMICONDUCTOR MFG4
Top patents by PatentIndex Score
4 records- 0182US6998335B2Structure and method for fabricating a bond pad structureCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted Feb 14, 2006·39 cites·25 claims
- 0281US7276797B2Structure and method for fabricating a bond pad structureCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Oct 2, 2007·12 cites·14 claims
- 0348US7148157B2Use of phoslon (PNO) for borderless contact fabrication, etch stop/barrier layer for dual damascene fabrication and method of forming phoslonCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Dec 12, 2006·3 cites·29 claims
- 0429US2004021997A1Novel ESD protection circuit for I/O circuitryCHARTERED SEMICONDUCTOR MFG·Filed 2002·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →