Inventor · disambiguated record
Raul A. Garibay, Jr.
Also filed as: GARIBAY JR RAUL A · GARIBAY RAUL · GARIBAY RAUL A · GARIBAY RAUL A JR
44 granted patents·5 pending applications·1,340 citations·filing 1992–2024
98Inventor score
Top patents by PatentIndex Score
49 records- 0197US11049586B2Systems and methods for implementing redundancy for tile-based intelligence processing computing architectureMYTHIC INC·Filed 2020·Granted Jun 29, 2021·8 cites·16 claims
- 0296US11016810B1Tile subsystem and method for automated data flow and data processing within an integrated circuit architectureMYTHIC INC·Filed 2020·Granted May 25, 2021·15 cites·15 claims
- 0394US11360932B2Systems and methods for implementing an intelligence processing computing architectureMYTHIC INC·Filed 2020·Granted Jun 14, 2022·5 cites·18 claims
- 0491US10521395B1Systems and methods for implementing an intelligence processing computing architectureMYTHIC INC·Filed 2019·Granted Dec 31, 2019·6 cites·16 claims
- 0590US6343363B1Method of invoking a low power mode in a computer system using a halt instructionNAT SEMICONDUCTOR CORP·Filed 2000·Granted Jan 29, 2002·40 cites·10 claims
- 0688US12013807B2Systems and methods for implementing an intelligence processing computing architectureMYTHIC INC·Filed 2022·Granted Jun 18, 2024·1 cites·18 claims
- 0788US5471598AData dependency detection and handling in a microprocessor with write bufferCYRIX CORP·Filed 1993·Granted Nov 28, 1995·139 cites·6 claims
- 0886US10606797B2Systems and methods for implementing an intelligence processing computing architectureMYTHIC INC·Filed 2019·Granted Mar 31, 2020·3 cites·12 claims
- 0982US5963984AAddress translation unit employing programmable page sizeNAT SEMICONDUCTOR CORP·Filed 1997·Granted Oct 5, 1999·100 cites·15 claims
- 1082US5907860ASystem and method of retiring store data from a write bufferNAT SEMICONDUCTOR CORP·Filed 1996·Granted May 25, 1999·90 cites·3 claims
- 1182US5630143AMicroprocessor with externally controllable power managementCYRIX CORP·Filed 1994·Granted May 13, 1997·81 cites·14 claims
- 1281US12461888B2Systems and methods for implementing an intelligence processing computing architectureMYTHIC INC·Filed 2024·Granted Nov 4, 2025·0 cites·16 claims
- 1379US6219773B1System and method of retiring misaligned write operands from a write bufferVIA CYRIX INC·Filed 1993·Granted Apr 17, 2001·79 cites·14 claims
- 1479US6138230AProcessor with multiple execution pipelines using pipe stage state information to control independent movement of instructions between pipe stages of an execution pipelineVIA CYRIX INC·Filed 1997·Granted Oct 24, 2000·88 cites·12 claims
- 1578US5524234ACoherency for write-back cache in a system designed for write-through cache including write-back latency controlCYRIX CORP·Filed 1994·Granted Jun 4, 1996·60 cites·13 claims
- 1678US2024311194A1Tile subsystem and method for automated data flow and data processing within an integrated circuit architectureMYTHIC INC·Filed 2024·Application pending·0 cites
- 1777US5584009ASystem and method of retiring store data from a write bufferCYRIX CORP·Filed 1993·Granted Dec 10, 1996·62 cites·16 claims
- 1877US5479616AException handling for prefetched instruction bytes using valid bits to identify instructions that will cause an exceptionCYRIX CORP·Filed 1992·Granted Dec 26, 1995·74 cites·11 claims
- 1974US5632037AMicroprocessor having power management circuitry with coprocessor supportCYRIX CORP·Filed 1992·Granted May 20, 1997·64 cites·8 claims
- 2073US7120810B2Instruction-initiated power management method for a pipelined data processorNAT SEMICONDUCTOR CORP·Filed 2004·Granted Oct 10, 2006·10 cites·82 claims
- 2172US6910141B2Pipelined data processor with signal-initiated power management controlNAT SEMICONDUCTOR CORP·Filed 2004·Granted Jun 21, 2005·9 cites·130 claims
- 2271US6088807AComputer system with low power mode invoked by halt instructionNAT SEMICONDUCTOR CORP·Filed 1996·Granted Jul 11, 2000·54 cites·9 claims
- 2370US10719651B2Synthesizing topology for an interconnect network of a system-on-chip with intellectual property blocksARTERIS INC·Filed 2017·Granted Jul 21, 2020·2 cites·16 claims
- 2470US7900076B2Power management method for a pipelined computer systemNAT SEMICONDUCTOR CORP·Filed 2007·Granted Mar 1, 2011·2 cites·12 claims
- 2570US7062666B2Signal-initiated method for suspending operation of a pipelined data processorNAT SEMICONDUCTOR CORP·Filed 2004·Granted Jun 13, 2006·8 cites·41 claims
- 2670US5752274AAddress translation unit employing a victim TLBCYRIX CORP·Filed 1994·Granted May 12, 1998·54 cites·14 claims
- 2769US12014214B2Tile subsystem and method for automated data flow and data processing within an integrated circuit architectureMYTHIC INC·Filed 2021·Granted Jun 18, 2024·0 cites·19 claims
- 2869US5860111ACoherency for write-back cache in a system designed for write-through cache including export-on-holdNAT SEMICONDUCTOR CORP·Filed 1995·Granted Jan 12, 1999·45 cites·14 claims
- 2968US6721894B2Method for controlling power of a microprocessor by asserting and de-asserting a control signal in response conditions associated with the microprocessor entering and exiting low power state respectivelyNAT SEMICONDUCTOR CORP·Filed 2002·Granted Apr 13, 2004·8 cites·42 claims
- 3068US5805879AIn a pipelined processor, setting a segment access indicator during execution stage using exception handlingCYRIX CORP·Filed 1996·Granted Sep 8, 1998·56 cites·12 claims
- 3167US7000132B2Signal-initiated power management method for a pipelined data processorNAT SEMICONDUCTOR CORP·Filed 2004·Granted Feb 14, 2006·6 cites·124 claims
- 3266US11475973B2Systems and methods for implementing redundancy for tile-based intelligence processing computing architectureMYTHIC INC·Filed 2021·Granted Oct 18, 2022·0 cites·20 claims
- 3363US5664149ACoherency for write-back cache in a system designed for write-through cache using an export/invalidate protocolCYRIX CORP·Filed 1993·Granted Sep 2, 1997·30 cites·6 claims
- 3462US7237065B2Configurable cache system depending on instruction typeTEXAS INSTRUMENTS INC·Filed 2005·Granted Jun 26, 2007·2 cites·28 claims
- 3559US5835949AMethod of identifying and self-modifying codeNAT SEMICONDUCTOR CORP·Filed 1997·Granted Nov 10, 1998·36 cites·16 claims
- 3657US6694443B1System for controlling power of a microprocessor by asserting and de-asserting a control signal in response to condition associated with the microprocessor entering and exiting low power state respectivelyNAT SEMICONDUCTOR CORP·Filed 2001·Granted Feb 17, 2004·4 cites·84 claims
- 3755US7900075B2Pipelined computer system with power management controlNAT SEMICONDUCTOR CORP·Filed 2007·Granted Mar 1, 2011·0 cites·14 claims
- 3854US5596735ACircuit and method for addressing segment descriptor tablesCYRIX CORP·Filed 1996·Granted Jan 21, 1997·28 cites·26 claims
- 3952US7085978B2Validating test signal connections within an integrated circuitADVANCED RISC MACH LTD·Filed 2002·Granted Aug 1, 2006·6 cites·16 claims
- 4052US5615402AUnified write buffer having information identifying whether the address belongs to a first write operand or a second write operand having an extra wide latchCYRIX CORP·Filed 1995·Granted Mar 25, 1997·27 cites·10 claims
- 4151US6978390B2Pipelined data processor with instruction-initiated power management controlNAT SEMICONDUCTOR CORP·Filed 2004·Granted Dec 20, 2005·2 cites·88 claims
- 4248US2011208950A1Processes, circuits, devices, and systems for scoreboard and other processor improvementsTEXAS INSTRUMENTS INC·Filed 2011·Application pending·0 cites
- 4348US2006095732A1Processes, circuits, devices, and systems for scoreboard and other processor improvementsTRAN THANG M·Filed 2005·Application pending·0 cites
- 4444US7509512B2Instruction-initiated method for suspending operation of a pipelined data processorNAT SEMICONDUCTOR CORP·Filed 2004·Granted Mar 24, 2009·0 cites·24 claims
- 4542US5572682AControl logic for a sequential data buffer using byte read-enable lines to define and shift the access windowCYRIX CORP·Filed 1992·Granted Nov 5, 1996·14 cites·8 claims
- 4642US2007028051A1Time and power reduction in cache accessesTEXAS INSTRUMENTS INC·Filed 2005·Application pending·0 cites
- 4740US5375209AMicroprocessor for selectively configuring pinout by activating tri-state device to disable internal clock from external pinCYRIX CORP·Filed 1992·Granted Dec 20, 1994·12 cites·8 claims
- 4839US5644741AProcessor with single clock decode architecture employing single microROMCYRIX CORP·Filed 1993·Granted Jul 1, 1997·10 cites·13 claims
- 4929US2006085707A1High speed energy conserving scan architectureTEXAS INSTRUMENTS INC·Filed 2004·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Raul A. Garibay, Jr. files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →