Inventor · disambiguated record
Douglas E. Duschatko
Also filed as: DUSCHATKO DOUGLAS E · DUSCHATKO DOUGLAS EWING
14 granted patents·715 citations·filing 1989–2002
95Inventor score
Top patents by PatentIndex Score
14 records- 0196US6982974B1Method and apparatus for a rearrangeably non-blocking switching matrixCISCO TECH IND·Filed 2000·Granted Jan 3, 2006·277 cites·35 claims
- 0286US6934305B1Method and apparatus for detecting errors in a backplane frameCISCO TECH IND·Filed 2000·Granted Aug 23, 2005·58 cites·81 claims
- 0384US7551640B1Method and apparatus for errorless frame timing adjustmentCISCO TECH INC·Filed 2002·Granted Jun 23, 2009·23 cites·35 claims
- 0483US6983414B1Error insertion circuit for SONET forward error correctionCISCO TECH IND·Filed 2001·Granted Jan 3, 2006·41 cites·39 claims
- 0579US6973041B1Path AIS insertion for concatenated payloads across multiple processorsCISCO TECH IND·Filed 2000·Granted Dec 6, 2005·17 cites·16 claims
- 0679US5644788ABurst transfers using an ascending or descending only burst orderingCYRIX CORP·Filed 1994·Granted Jul 1, 1997·86 cites·6 claims
- 0778US5524234ACoherency for write-back cache in a system designed for write-through cache including write-back latency controlCYRIX CORP·Filed 1994·Granted Jun 4, 1996·60 cites·13 claims
- 0874US6801548B1Channel ordering for communication signals split for matrix switchingCISCO TECH IND·Filed 2000·Granted Oct 5, 2004·12 cites·33 claims
- 0969US5860111ACoherency for write-back cache in a system designed for write-through cache including export-on-holdNAT SEMICONDUCTOR CORP·Filed 1995·Granted Jan 12, 1999·45 cites·14 claims
- 1065US5146461AMemory error correction system distributed on a high performance multiprocessor bus and method thereforSOLBOURNE COMPUTER INC·Filed 1989·Granted Sep 8, 1992·36 cites·13 claims
- 1163US5664149ACoherency for write-back cache in a system designed for write-through cache using an export/invalidate protocolCYRIX CORP·Filed 1993·Granted Sep 2, 1997·30 cites·6 claims
- 1261US6735197B1Concatenation detection across multiple chipsCISCO TECH IND·Filed 2000·Granted May 11, 2004·8 cites·21 claims
- 1343US5878269AHigh speed processor for operation at reduced operating voltageNAT SEMICONDUCTOR CORP·Filed 1992·Granted Mar 2, 1999·8 cites·11 claims
- 1442US5572682AControl logic for a sequential data buffer using byte read-enable lines to define and shift the access windowCYRIX CORP·Filed 1992·Granted Nov 5, 1996·14 cites·8 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →