Inventor · disambiguated record
Marvin W. Martinez, Jr.
Also filed as: MARTINEZ JR MARVIN W · MARTINEZ JR MARVIN WAYNE
12 granted patents·263 citations·filing 1993–2012
92Inventor score
Top patents by PatentIndex Score
12 records- 0180US7421637B1Generating test input for a circuitCISCO TECH INC·Filed 2003·Granted Sep 2, 2008·27 cites·23 claims
- 0278US5524234ACoherency for write-back cache in a system designed for write-through cache including write-back latency controlCYRIX CORP·Filed 1994·Granted Jun 4, 1996·60 cites·13 claims
- 0369US5860111ACoherency for write-back cache in a system designed for write-through cache including export-on-holdNAT SEMICONDUCTOR CORP·Filed 1995·Granted Jan 12, 1999·45 cites·14 claims
- 0464US9256548B2Rule-based virtual address translation for accessing dataSTEISS DONALD EDWARD·Filed 2012·Granted Feb 9, 2016·2 cites·20 claims
- 0563US5664149ACoherency for write-back cache in a system designed for write-through cache using an export/invalidate protocolCYRIX CORP·Filed 1993·Granted Sep 2, 1997·30 cites·6 claims
- 0661US5611071ASplit replacement cycles for sectored cache lines in a 64-bit microprocessor interfaced to a 32-bit bus architectureCYRIX CORP·Filed 1995·Granted Mar 11, 1997·42 cites·20 claims
- 0746US5742184AMicroprocessor having a compensated input buffer circuitCYRIX CORP·Filed 1996·Granted Apr 21, 1998·9 cites·5 claims
- 0844US5898815AI/O bus interface recovery counter dependent upon minimum bus clocks to prevent overrun and ratio of execution core clock frequency to system bus clock frequencyNAT SEMICONDUCTOR CORP·Filed 1996·Granted Apr 27, 1999·17 cites·15 claims
- 0944US5596731ASingle clock bus transfers during burst and non-burst cyclesCYRIX CORP·Filed 1995·Granted Jan 21, 1997·18 cites·18 claims
- 1040US7047432B1Method and system for synchronizing output from differently timed circuitsCISCO TECH INC·Filed 2003·Granted May 16, 2006·1 cites·16 claims
- 1138US7116740B1Method and system for providing clock signalsCISCO TECH INC·Filed 2003·Granted Oct 3, 2006·2 cites·22 claims
- 1232US6122696ACPU-peripheral bus interface using byte enable signaling to control byte lane steeringFiled 1997·Granted Sep 19, 2000·10 cites·4 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →