Inventor · disambiguated record
Sanjiv Taneja
Also filed as: TANEJA SANJIV
8 granted patents·270 citations·filing 1995–2015
90Inventor score
Top patents by PatentIndex Score
8 records- 0196US9564884B1Circuitry and method for measuring negative bias temperature instability (NBTI) and hot carrier injection (HCI) aging effects using edge sensitive samplingAbreezio LLC·Filed 2015·Granted Feb 7, 2017·37 cites·20 claims
- 0296US9536038B1Method and algorithm for functional critical paths selection and critical path sensors and controller insertionAbreezio LLC·Filed 2015·Granted Jan 3, 2017·52 cites·18 claims
- 0396US9529044B1Apparatuses and methods to enhance timing delay fault coverageAbreezio LLC·Filed 2015·Granted Dec 27, 2016·22 cites·20 claims
- 0495US9760672B1Circuitry and method for critical path timing speculation to enable process variation compensation via voltage scalingQUALCOMM INC·Filed 2015·Granted Sep 12, 2017·63 cites·18 claims
- 0595US9564883B1Circuitry and method for timing speculation via toggling functional critical pathsAbreezio LLC·Filed 2015·Granted Feb 7, 2017·39 cites·20 claims
- 0690US9536625B1Circuitry and method for critical path timing speculation in RAMsAbreezio LLC·Filed 2015·Granted Jan 3, 2017·14 cites·30 claims
- 0788US9535121B1Methods and apparatuses to enhance timing delay fault coverage with test logic that includes partitions and scan flip-flopsAbreezio LLC·Filed 2015·Granted Jan 3, 2017·4 cites·19 claims
- 0855US5633807ASystem and method for generating mask layoutsLUCENT TECHNOLOGIES INC·Filed 1995·Granted May 27, 1997·39 cites·21 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →