Inventor · disambiguated record
Adrian C. Moga
Also filed as: MOGA ADRIAN · MOGA ADRIAN C
21 granted patents·4 pending applications·141 citations·filing 2001–2022
93Inventor score
Top patents by PatentIndex Score
25 records- 0194US8838935B2Apparatus, method, and system for implementing micro page tablesHINTON GLENN·Filed 2010·Granted Sep 16, 2014·79 cites·25 claims
- 0293US12271306B2Integrated three-dimensional (3D) DRAM cacheINTEL CORP·Filed 2021·Granted Apr 8, 2025·3 cites·20 claims
- 0383US9418009B2Inclusive and non-inclusive tracking of local cache lines to avoid near memory reads on cache line memory writes into a two level system memoryINTEL CORP·Filed 2013·Granted Aug 16, 2016·7 cites·21 claims
- 0483US8392665B2Allocation and write policy for a glueless area-efficient directory cache for hotly contested cache linesMOGA ADRIAN C·Filed 2010·Granted Mar 5, 2013·12 cites·30 claims
- 0580US10725920B2Processors having virtually clustered cores and cache slicesINTEL CORP·Filed 2018·Granted Jul 28, 2020·2 cites·26 claims
- 0680US10705960B2Processors having virtually clustered cores and cache slicesINTEL CORP·Filed 2018·Granted Jul 7, 2020·2 cites·21 claims
- 0779US8041898B2Method, system and apparatus for reducing memory traffic in a distributed memory systemINTEL CORP·Filed 2008·Granted Oct 18, 2011·10 cites·15 claims
- 0875US10725919B2Processors having virtually clustered cores and cache slicesINTEL CORP·Filed 2018·Granted Jul 28, 2020·1 cites·22 claims
- 0970US9792212B2Virtual shared cache mechanism in a processing deviceINTEL CORP·Filed 2014·Granted Oct 17, 2017·2 cites·20 claims
- 1068US9081688B2Obtaining data for redundant multithreading (RMT) executionHINTON GLENN J·Filed 2008·Granted Jul 14, 2015·4 cites·15 claims
- 1167US6848026B2Caching memory contents into cache partitions based on memory locationsIBM·Filed 2001·Granted Jan 25, 2005·13 cites·20 claims
- 1266US10073779B2Processors having virtually clustered cores and cache slicesINTEL CORP·Filed 2012·Granted Sep 11, 2018·1 cites·21 claims
- 1362US11513957B2Processor and method implementing a cacheline demote machine instructionINTEL CORP·Filed 2020·Granted Nov 29, 2022·0 cites·20 claims
- 1458US12417182B2De-prioritizing speculative code lines in on-chip cachesINTEL CORP·Filed 2021·Granted Sep 16, 2025·0 cites·21 claims
- 1558US6807586B2Increased computer peripheral throughput by using data available withholdingIBM·Filed 2002·Granted Oct 19, 2004·5 cites·14 claims
- 1657US10817425B2Hardware/software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloadsINTEL CORP·Filed 2014·Granted Oct 27, 2020·0 cites·12 claims
- 1753US12327045B2System, apparatus, and method for scheduling metadata requestsINTEL CORP·Filed 2021·Granted Jun 10, 2025·0 cites·17 claims
- 1853US8631210B2Allocation and write policy for a glueless area-efficient directory cache for hotly contested cache linesINTEL CORP·Filed 2013·Granted Jan 14, 2014·0 cites·20 claims
- 1950US9436605B2Cache coherency apparatus and method minimizing memory writeback operationsINTEL CORP·Filed 2013·Granted Sep 6, 2016·0 cites·19 claims
- 2048US2023105491A1Cloud service mesh performance tuningINTEL CORP·Filed 2022·Application pending·0 cites
- 2147US7552247B2Increased computer peripheral throughput by using data available withholdingIBM·Filed 2004·Granted Jun 23, 2009·0 cites·4 claims
- 2244US9015415B2Multi-processor computing system having fast processor response to cache agent request capacity limit warningVARMA ANKUSH·Filed 2010·Granted Apr 21, 2015·0 cites·20 claims
- 2344US2010332762A1Directory cache allocation based on snoop response informationMOGA ADRIAN C·Filed 2009·Application pending·0 cites
- 2444US2023091205A1Memory side prefetch architecture for improved memory bandwidthINTEL CORP·Filed 2021·Application pending·0 cites
- 2543US2005193177A1Selectively transmitting cache misses within coherence protocolFiled 2004·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →