Inventor · disambiguated record
Jyh-Min Jiang
Also filed as: JIANG JYH-MIN
6 granted patents·121 citations·filing 1999–2002
84Inventor score
Top patents by PatentIndex Score
6 records- 0188US6323074B1High voltage ESD protection device with very low snapback voltage by adding as a p+ diffusion and n-well to the NMOS drainTAIWAN SEMICONDUCTOR MFG·Filed 2000·Granted Nov 27, 2001·44 cites·5 claims
- 0277US6265752B1Method of forming a HVNMOS with an N+ buried layer combined with N well and a structure of the sameTAIWAN SEMICONDUCTOR MFG CO IN·Filed 1999·Granted Jul 24, 2001·51 cites·7 claims
- 0357US6590262B2High voltage ESD protection device with very low snapback voltageTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Jul 8, 2003·7 cites·10 claims
- 0444US6396126B1High voltage transistor using P+ buried layerTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted May 28, 2002·2 cites·12 claims
- 0542US6242313B1Use of polysilicon field plates to improve high voltage bipolar device breakdown voltageTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Jun 5, 2001·12 cites·19 claims
- 0638US6291304B1Method of fabricating a high voltage transistor using P+ buried layerTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Sep 18, 2001·5 cites·8 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →