Inventor · disambiguated record
Alexander Ishii
Also filed as: ISHII ALEXANDER · ISHII ALEXANDER T · ISHII ALEXANDER TOICHI
19 granted patents·1 pending application·575 citations·filing 1993–2020
96Inventor score
Files withCYCLOS SEMICONDUCTOR INC6PAPAEFTHYMIOU MARIOS C5NEC USA INC4NVIDIA CORP3ISHII ALEXANDER T1
Top patents by PatentIndex Score
20 records- 0197US8659338B2Resonant clock distribution network architecture with programmable driversPAPAEFTHYMIOU MARIOS C·Filed 2010·Granted Feb 25, 2014·19 cites·23 claims
- 0297US8502569B2Architecture for operating resonant clock network in conventional modePAPAEFTHYMIOU MARIOS C·Filed 2010·Granted Aug 6, 2013·22 cites·18 claims
- 0397US8339209B2Method for selecting natural frequency in resonant clock distribution networks with no inductor overheadPAPAEFTHYMIOU MARIOS C·Filed 2010·Granted Dec 25, 2012·18 cites·16 claims
- 0496US8368450B2Architecture for adjusting natural frequency in resonant clock distribution networksCYCLOS SEMICONDUCTOR INC·Filed 2010·Granted Feb 5, 2013·17 cites·13 claims
- 0594US11882678B2Redundant isolation of rack manifolds for datacenter cooling systemsNVIDIA CORP·Filed 2020·Granted Jan 23, 2024·4 cites·24 claims
- 0694US8400192B2Architecture for frequency-scaled operation in resonant clock distribution networksPAPAEFTHYMIOU MARIOS C·Filed 2010·Granted Mar 19, 2013·18 cites·15 claims
- 0794US8362811B2Architecture for single-stepping in resonant clock distribution networksCYCLOS SEMICONDUCTOR INC·Filed 2010·Granted Jan 29, 2013·19 cites·15 claims
- 0894US8358163B2Resonant clock distribution network architecture for tracking parameter variations in conventional clock distribution networksCYCLOS SEMICONDUCTOR INC·Filed 2010·Granted Jan 22, 2013·11 cites·1 claims
- 0993US9041451B2Resonant clock distribution network architecture for tracking parameter variations in conventional clock distribution networksCYCLOS SEMICONDUCTOR INC·Filed 2012·Granted May 26, 2015·8 cites·19 claims
- 1093US8593183B2Architecture for controlling clock characteristicsPAPAEFTHYMIOU MARIOS C·Filed 2010·Granted Nov 26, 2013·15 cites·17 claims
- 1193US7973565B2Resonant clock and interconnect architecture for digital devices with multiple clock networksCYCLOS SEMICONDUCTOR INC·Filed 2008·Granted Jul 5, 2011·31 cites·26 claims
- 1288US8461873B2Resonant clock and interconnect architecture for digital devices with multiple clock networksISHII ALEXANDER T·Filed 2011·Granted Jun 11, 2013·16 cites·26 claims
- 1384US5448567AControl architecture for ATM networksNEC RESEARCH INST INC·Filed 1993·Granted Sep 5, 1995·124 cites·5 claims
- 1483US10769076B2Distributed address translation in a multi-node interconnect fabricNVIDIA CORP·Filed 2018·Granted Sep 8, 2020·3 cites·21 claims
- 1576US6389019B1Time-based scheduler architecture and method for ATM networksNEC USA INC·Filed 1998·Granted May 14, 2002·106 cites·30 claims
- 1673US6556571B1Fast round robin priority port scheduler for high capacity ATM switchesNEC USA INC·Filed 1999·Granted Apr 29, 2003·80 cites·18 claims
- 1761US11327900B2Securing memory accesses in a virtualized environmentNVIDIA CORP·Filed 2020·Granted May 10, 2022·0 cites·20 claims
- 1859US6424622B1Optimal buffer management scheme with dynamic queue length thresholds for ATM switchesNEC USA INC·Filed 1999·Granted Jul 23, 2002·41 cites·9 claims
- 1957US2013194018A1Method for Selecting Natural Frequency in Resonant Clock Distribution Networks with no Inductor OverheadCYCLOS SEMICONDUCTOR INC·Filed 2012·Application pending·0 cites
- 2050US5644499ARetiming gated-clocks and precharged circuit structuresNEC USA INC·Filed 1995·Granted Jul 1, 1997·23 cites·16 claims
Join the waitlist — get patent alerts
Get an alert when Alexander Ishii files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →