Inventor · disambiguated record
Lijiang Wang
Also filed as: WANG LIJIANG · WANG LIJIANG L
14 granted patents·6 pending applications·58 citations·filing 1995–2024
89Inventor score
Files withINTEL CORP6SHENZHEN PHARMACIN CO LTD5IBM3KEMERER DOUGLAS W2SHANGHAI BIXIUFU ENTERPRISE MAN CO LTD2
Top patents by PatentIndex Score
20 records- 0185US11083721B2Preparation method thereforSHENZHEN PHARMACIN CO LTD·Filed 2019·Granted Aug 10, 2021·2 cites·16 claims
- 0283US2025221975A1Pharmaceutical composition and preparation method thereforSHENZHEN PHARMACIN CO LTD·Filed 2024·Application pending·0 cites
- 0380US10159664B2Pharmaceutical composition and preparation method thereforSHENZHEN PHARMACIN CO LTD·Filed 2017·Granted Dec 25, 2018·3 cites·7 claims
- 0477US11869842B2Scalable high speed high bandwidth IO signaling package architecture and method of makingINTEL CORP·Filed 2019·Granted Jan 9, 2024·2 cites·17 claims
- 0574US7076749B2Method and system for improving integrated circuit manufacturing productivityIBM·Filed 2004·Granted Jul 11, 2006·22 cites·20 claims
- 0672US12133847B2Pharmaceutical composition and preparation method thereforSHENZHEN PHARMACIN CO LTD·Filed 2021·Granted Nov 5, 2024·0 cites·21 claims
- 0772US8191030B2Identifying parasitic diode(s) in an integrated circuit physical designKEMERER DOUGLAS W·Filed 2008·Granted May 29, 2012·5 cites·19 claims
- 0869US10864204B2Pharmaceutical composition and preparation method thereforSHENZHEN PHARMACIN CO LTD·Filed 2018·Granted Dec 15, 2020·0 cites·21 claims
- 0969US2024088047A1Scalable high speed high bandwidth io signaling package architecture and method of makingINTEL CORP·Filed 2023·Application pending·0 cites
- 1066US8799836B1Yield optimization for design library elements at library element level or at product levelIBM·Filed 2013·Granted Aug 5, 2014·2 cites·20 claims
- 1159US5731411APromotion of homologous DNA pairing by RecA-derived peptidesUS HEALTH·Filed 1995·Granted Mar 24, 1998·22 cites·3 claims
- 1256US2024332193A1Interconnect bridge circuitry designs for integrated circuit package substratesINTEL CORP·Filed 2023·Application pending·0 cites
- 1355US11114394B2Signal routing carrierINTEL CORP·Filed 2019·Granted Sep 7, 2021·0 cites·10 claims
- 1453US2024006323A1Interconnect bridge with similar channel lengthsINTEL CORP·Filed 2022·Application pending·0 cites
- 1550US12057413B2Package design scheme for enabling high-speed low-loss signaling and mitigation of manufacturing risk and costINTEL CORP·Filed 2019·Granted Aug 6, 2024·0 cites·21 claims
- 1649US8756554B2Identifying parasitic diode(s) in an integrated circuit physical designKEMERER DOUGLAS W·Filed 2012·Granted Jun 17, 2014·0 cites·19 claims
- 1749US7490303B2Identifying parasitic diode(s) in an integrated circuit physical designIBM·Filed 2006·Granted Feb 10, 2009·0 cites·3 claims
- 1846US11281105B2Light generation method and systemSHANGHAI BIXIUFU ENTERPRISE MAN CO LTD·Filed 2018·Granted Mar 22, 2022·0 cites·20 claims
- 1946US2021038444A1Feminine hygiene pad and method for isolating microorganisms from a wearer's skinPROCTER & GAMBLE·Filed 2020·Application pending·0 cites
- 2036US2020341373A1Lithographic Method, Lithographic Product and Lithographic MaterialSHANGHAI BIXIUFU ENTERPRISE MAN CO LTD·Filed 2018·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →