Inventor · disambiguated record
Jenn Tsao
Also filed as: TSAO JENN
15 granted patents·691 citations·filing 1993–2001
95Inventor score
Files withTAIWAN SEMICONDUCTOR MFG7UNITED MICROELECTRONICS CORP4BERG TECH INC2FCI AMERICAS TECHNOLOGY INC1
Top patents by PatentIndex Score
15 records- 0197US5456619AFiltered modular jack assembly and method of useBERG TECH INC·Filed 1994·Granted Oct 10, 1995·192 cites·30 claims
- 0293US6080011AStacked double deck modular gang jack connectorBERG TECH INC·Filed 1998·Granted Jun 27, 2000·80 cites·13 claims
- 0392US5817562AMethod for making improved polysilicon FET gate electrode structures and sidewall spacers for more reliable self-aligned contacts (SAC)TAIWAN SEMICONDUCTOR MFG·Filed 1997·Granted Oct 6, 1998·147 cites·24 claims
- 0484US6358094B1Low inductance connector with enhanced capacitively coupled contacts for power applicationsFCI AMERICAS TECHNOLOGY INC·Filed 2000·Granted Mar 19, 2002·33 cites·21 claims
- 0583US5766992AProcess for integrating a MOSFET device, using silicon nitride spacers and a self-aligned contact structure, with a capacitor structureTAIWAN SEMICONDUCTOR MFG·Filed 1997·Granted Jun 16, 1998·60 cites·24 claims
- 0680US6017795AMethod of fabricating buried source to shrink cell dimension and increase coupling ratio in split-gate flashTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Jan 25, 2000·37 cites·29 claims
- 0780US5731236AProcess to integrate a self-aligned contact structure, with a capacitor structureTAIWAN SEMICONDUCTOR MFG·Filed 1997·Granted Mar 24, 1998·49 cites·22 claims
- 0871US6124609ASplit gate flash memory with buried source to shrink cell dimension and increase coupling ratioTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Sep 26, 2000·22 cites·4 claims
- 0964US6083783AMethod of manufacturing complementary metallic-oxide-semiconductorUNITED MICROELECTRONICS CORP·Filed 1998·Granted Jul 4, 2000·24 cites·18 claims
- 1052US6136713AMethod for forming a shallow trench isolation structureUNITED MICROELECTRONICS CORP·Filed 1998·Granted Oct 24, 2000·17 cites·20 claims
- 1148US6133083AMethod to fabricate embedded DRAMUNITED MICROELECTRONICS CORP·Filed 1998·Granted Oct 17, 2000·9 cites·9 claims
- 1247US6207515B1Method of fabricating buried source to shrink chip size in memory arrayTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Mar 27, 2001·12 cites·16 claims
- 1339US6396112B2Method of fabricating buried source to shrink chip size in memory arrayTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted May 28, 2002·0 cites·5 claims
- 1436US5538448AGang modular jackFiled 1993·Granted Jul 23, 1996·7 cites·15 claims
- 1532US6291111B1Method of trench polishingUNITED MICROELECTRONICS CORP·Filed 1998·Granted Sep 18, 2001·2 cites·3 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →