Inventor · disambiguated record
Steven C. Mcmahan
Also filed as: MCMAHAN STEVEN C · MCMAHAN STEVEN CRAIG
19 granted patents·856 citations·filing 1989–2005
96Inventor score
Top patents by PatentIndex Score
19 records- 0195US5162672AData processor having an output terminal with selectable output impedancesMOTOROLA INC·Filed 1990·Granted Nov 10, 1992·84 cites·13 claims
- 0282US5859541AData processor having an output terminal with selectable output impedancesMOTOROLA INC·Filed 1993·Granted Jan 12, 1999·30 cites·16 claims
- 0381US5835951ABranch processing unit with target cache read prioritization protocol for handling multiple hitsNAT SEMICONDUCTOR CORP·Filed 1996·Granted Nov 10, 1998·103 cites·3 claims
- 0479US6138230AProcessor with multiple execution pipelines using pipe stage state information to control independent movement of instructions between pipe stages of an execution pipelineVIA CYRIX INC·Filed 1997·Granted Oct 24, 2000·88 cites·12 claims
- 0579US5706491ABranch processing unit with a return stack including repair using pointers from different pipe stagesCYRIX CORP·Filed 1996·Granted Jan 6, 1998·91 cites·6 claims
- 0679US5294845AData processor having an output terminal with selectable output impedancesMOTOROLA INC·Filed 1992·Granted Mar 15, 1994·27 cites·14 claims
- 0778US5835967AAdjusting prefetch size based on source of prefetch addressCYRIX CORP·Filed 1996·Granted Nov 10, 1998·89 cites·9 claims
- 0877US5692168APrefetch buffer using flow control bit to identify changes of flow within the code streamCYRIX CORP·Filed 1996·Granted Nov 25, 1997·83 cites·5 claims
- 0969US7490276B1Testing self-repairing memory of a deviceCISCO TECH INC·Filed 2005·Granted Feb 10, 2009·6 cites·6 claims
- 1069US7007211B1Testing self-repairing memory of a deviceCISCO TECH IND·Filed 2002·Granted Feb 28, 2006·15 cites·18 claims
- 1166US5086407AData processor integrated circuit with selectable multiplexed/non-multiplexed address and data modes of operationMCGARITY RALPH C·Filed 1989·Granted Feb 4, 1992·42 cites·9 claims
- 1261US5732243ABranch processing unit with target cache using low/high banking to support split prefetchingCYRIX CORP·Filed 1996·Granted Mar 24, 1998·40 cites·6 claims
- 1359US5835949AMethod of identifying and self-modifying codeNAT SEMICONDUCTOR CORP·Filed 1997·Granted Nov 10, 1998·36 cites·16 claims
- 1455US5732253ABranch processing unit with target cache storing history for predicted taken branches and history cache storing history for predicted not-taken branchesCYRIX CORP·Filed 1996·Granted Mar 24, 1998·31 cites·8 claims
- 1552US5337269ACarry skip adder with independent carry-in and carry skip pathsCYRIX CORP·Filed 1993·Granted Aug 9, 1994·24 cites·18 claims
- 1651US5771365ACondensed microaddress generation in a complex instruction set computerCYRIX CORP·Filed 1995·Granted Jun 23, 1998·24 cites·8 claims
- 1750US5740416ABranch processing unit with a far target cache accessed by indirection from the target cacheCYRIX CORP·Filed 1996·Granted Apr 14, 1998·24 cites·6 claims
- 1839US5644741AProcessor with single clock decode architecture employing single microROMCYRIX CORP·Filed 1993·Granted Jul 1, 1997·10 cites·13 claims
- 1937US5784713AAddress calculation logic including limit checking using carry out to flag limit violationCYRIX CORP·Filed 1993·Granted Jul 21, 1998·9 cites·12 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →