Inventor · disambiguated record
Anil Aggarwal
Also filed as: AGGARWAL ANIL · AGGARWAL ANIL DATT
33 granted patents·3 pending applications·343 citations·filing 2001–2019
97Inventor score
Top patents by PatentIndex Score
36 records- 0197US7818596B2Method and apparatus of power management of processorINTEL CORP·Filed 2006·Granted Oct 19, 2010·53 cites·18 claims
- 0296US7328293B2Queued locks using monitor-memory waitINTEL CORP·Filed 2007·Granted Feb 5, 2008·47 cites·21 claims
- 0392US9081707B2Apparatus and method for tracking TLB flushes on a per thread basisCONRAD SHAUN M·Filed 2012·Granted Jul 14, 2015·26 cites·21 claims
- 0492US7962771B2Method, system, and apparatus for rerouting interrupts in a multi-core processorINTEL CORP·Filed 2007·Granted Jun 14, 2011·28 cites·28 claims
- 0588US9720730B2Providing an asymmetric multicore processor system transparently to an operating systemGINZBURG BORIS·Filed 2011·Granted Aug 1, 2017·15 cites·20 claims
- 0687US8479217B2Apparatus, system, and method for persistent user-level threadCHINYA GAUTHAM·Filed 2011·Granted Jul 2, 2013·7 cites·19 claims
- 0787US8458498B2Method and apparatus of power management of processorROTEM EFRAIM·Filed 2008·Granted Jun 4, 2013·14 cites·22 claims
- 0886US10372197B2User level control of power management policiesINTEL CORP·Filed 2016·Granted Aug 6, 2019·3 cites·20 claims
- 0986US7849465B2Programmable event driven yield mechanism which may activate service threadsINTEL CORP·Filed 2005·Granted Dec 7, 2010·18 cites·24 claims
- 1085US7917789B2System and method for selecting optimal processor performance levels by using processor hardware feedback mechanismsINTEL CORP·Filed 2007·Granted Mar 29, 2011·15 cites·21 claims
- 1184US9442739B2Collaborative processor and system performance and power managementTHERIEN GUY M·Filed 2011·Granted Sep 13, 2016·4 cites·10 claims
- 1284US7640384B2Queued locks using monitor-memory waitINTEL CORP·Filed 2007·Granted Dec 29, 2009·10 cites·21 claims
- 1382US9454379B2Collaborative processor and system performance and power managementTHERIEN GUY M·Filed 2011·Granted Sep 27, 2016·3 cites·18 claims
- 1481US10185566B2Migrating tasks between asymmetric computing elements of a multi-core processorNAVEH ALON·Filed 2012·Granted Jan 22, 2019·5 cites·19 claims
- 1580US10275260B2Collaborative processor and system performance and power managementINTEL CORP·Filed 2016·Granted Apr 30, 2019·1 cites·18 claims
- 1680US9098261B2User level control of power management policiesSISTLA KRISHNAKANTH V·Filed 2011·Granted Aug 4, 2015·4 cites·16 claims
- 1780US7213093B2Queued locks using monitor-memory waitINTEL CORP·Filed 2003·Granted May 1, 2007·22 cites·14 claims
- 1879US8874947B2Method and apparatus of power management of processorINTEL CORP·Filed 2013·Granted Oct 28, 2014·4 cites·17 claims
- 1978US9170624B2User level control of power management policiesINTEL CORP·Filed 2013·Granted Oct 27, 2015·3 cites·18 claims
- 2078US7810083B2Mechanism to emulate user-level multithreading on an OS-sequestered sequencerINTEL CORP·Filed 2004·Granted Oct 5, 2010·25 cites·37 claims
- 2174US8028295B2Apparatus, system, and method for persistent user-level threadINTEL CORP·Filed 2005·Granted Sep 27, 2011·4 cites·21 claims
- 2274US7194540B2Mechanism for allowing multiple entities on the same host to handle messages of same service class in a clusterINTEL CORP·Filed 2001·Granted Mar 20, 2007·21 cites·20 claims
- 2373US10007528B2Computing platform interface with memory managementINTEL CORP·Filed 2012·Granted Jun 26, 2018·1 cites·19 claims
- 2473US8719819B2Mechanism for instruction set based thread execution on a plurality of instruction sequencersWANG HONG·Filed 2005·Granted May 6, 2014·4 cites·20 claims
- 2572US11221857B2Collaborative processor and system performance and power managementINTEL CORP·Filed 2019·Granted Jan 11, 2022·0 cites·19 claims
- 2672US9535487B2User level control of power management policiesINTEL CORP·Filed 2015·Granted Jan 3, 2017·1 cites·20 claims
- 2760US9875102B2Apparatus, system, and method for persistent user-level threadINTEL CORP·Filed 2016·Granted Jan 23, 2018·0 cites·20 claims
- 2859US9766891B2Apparatus, system, and method for persistent user-level threadINTEL CORP·Filed 2016·Granted Sep 19, 2017·0 cites·20 claims
- 2959US2017010895A1Mechanism for instruction set based thread execution on a plurality of instruction sequencersINTEL CORP·Filed 2016·Application pending·0 cites
- 3058US10108433B2Collaborative processor and system performance and power managementTHERIEN GUY M·Filed 2011·Granted Oct 23, 2018·0 cites·19 claims
- 3157US9383997B2Apparatus, system, and method for persistent user-level threadINTEL CORP·Filed 2013·Granted Jul 5, 2016·0 cites·20 claims
- 3255US9720697B2Mechanism for instruction set based thread execution on a plurality of instruction sequencersWANG HONG·Filed 2012·Granted Aug 1, 2017·0 cites·18 claims
- 3353US9459683B2Techniques for entering a low power stateINTEL CORP·Filed 2013·Granted Oct 4, 2016·0 cites·22 claims
- 3452US8984199B2Inter-processor interruptsHAMMARLUND PER·Filed 2003·Granted Mar 17, 2015·5 cites·15 claims
- 3549US2017249008A1Techniques for entering a low power stateINTEL CORP·Filed 2016·Application pending·0 cites
- 3640US2010228683A1Issuing systems, acquiring systems, and payment networks/systems developmentTXVIA INC·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →