Inventor · disambiguated record
Perrine Batude
Also filed as: BATUDE PERRINE
24 granted patents·3 pending applications·712 citations·filing 2009–2021
94Inventor score
Files withCOMMISSARIAT ENERGIE ATOMIQUE19COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT2ST MICROELECTRONICS SA2AUGENDRE EMMANUEL1BATUDE PERRINE1
Top patents by PatentIndex Score
27 records- 0198US8013399B2SRAM memory cell having transistors integrated at several levels and the threshold voltage VT of which is dynamically adjustableCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2009·Granted Sep 6, 2011·232 cites·21 claims
- 0296US8853785B2Integrated circuit with electrostatically coupled MOS transistors and method for producing such an integrated circuitAUGENDRE EMMANUEL·Filed 2010·Granted Oct 7, 2014·182 cites·10 claims
- 0395US8183630B2Circuit with transistors integrated in three dimensions and having a dynamically adjustable threshold voltage VTBATUDE PERRINE·Filed 2009·Granted May 22, 2012·261 cites·19 claims
- 0492US11658260B2Method of manufacturing an optoelectronic device comprising a plurality of diodesCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2021·Granted May 23, 2023·2 cites·16 claims
- 0589US9502566B2Method for producing a field effect transistor including forming a gate after forming the source and drainCOMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT·Filed 2014·Granted Nov 22, 2016·9 cites·30 claims
- 0683US9246006B2Recrystallization of source and drain blocks from aboveCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2014·Granted Jan 26, 2016·6 cites·7 claims
- 0782US9343375B2Method for manufacturing a transistor in which the strain applied to the channel is increasedCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2015·Granted May 17, 2016·4 cites·19 claims
- 0879US9966453B2Method for doping source and drain regions of a transistor by means of selective amorphisationCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2016·Granted May 8, 2018·3 cites·13 claims
- 0975US9018078B2Method of making a 3D integrated circuitST MICROELECTRONICS SA·Filed 2013·Granted Apr 28, 2015·4 cites·20 claims
- 1074US9379213B2Method for forming doped areas under transistor spacersCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2014·Granted Jun 28, 2016·3 cites·16 claims
- 1171US10170621B2Method of making a transistor having a source and a drain obtained by recrystallization of semiconductorCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2017·Granted Jan 1, 2019·2 cites·15 claims
- 1271US9761607B2Method for producing strained semi-conductor blocks on the insulating layer of a semi-conductor on insulator substrateCOMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT·Filed 2014·Granted Sep 12, 2017·2 cites·10 claims
- 1367US10586740B2Method for manufacturing pairs of CMOS transistors of the “fin-FET” type at low temperaturesCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2018·Granted Mar 10, 2020·1 cites·13 claims
- 1462US8722471B2Method for forming a via contacting several levels of semiconductor layersST MICROELECTRONICS SA·Filed 2013·Granted May 13, 2014·1 cites·8 claims
- 1553US12154930B2Three-dimensional microelectronic circuit with optimised distribution of its digital and analogue functionsCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2021·Granted Nov 26, 2024·0 cites·16 claims
- 1648US11011425B2Production of a 3D circuit with upper level transistor provided with a gate dielectric derived from a substrate transferCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2019·Granted May 18, 2021·0 cites·21 claims
- 1747US11552125B2Method of manufacturing an optoelectronic device comprising a plurality of diodes and an electronic circuit for controlling these diodesCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2019·Granted Jan 10, 2023·0 cites·15 claims
- 1847US11139209B23D circuit provided with mesa isolation for the ground plane zoneCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2019·Granted Oct 5, 2021·0 cites·8 claims
- 1947US10651202B23D circuit transistors with flipped gateCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2018·Granted May 12, 2020·0 cites·12 claims
- 2044US11888007B2Image sensor formed in sequential 3D technologyCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2020·Granted Jan 30, 2024·0 cites·15 claims
- 2143US9779982B2Fabrication method of a stack of electronic devicesCommissariat à l'Energie Atomique et aux Energies Alternatives·Filed 2016·Granted Oct 3, 2017·0 cites·14 claims
- 2243US2019148367A13d circuit with n and p junctionless transistorsCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2018·Application pending·0 cites
- 2340US10319628B2Integrated circuit having a plurality of active layers and method of fabricating the sameCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2017·Granted Jun 11, 2019·0 cites·10 claims
- 2438US10553702B2Transistor with controlled overlap of access regionsCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2017·Granted Feb 4, 2020·0 cites·7 claims
- 2537US10497627B2Method of manufacturing a dopant transistor located vertically on the gateCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2017·Granted Dec 3, 2019·0 cites·17 claims
- 2637US2013203248A1Integrated circuit having a junctionless depletion-mode fet deviceERNST THOMAS·Filed 2011·Application pending·0 cites
- 2733US2016181155A1Method for making an integrated circuit in three dimensionsCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →