Inventor · disambiguated record
James E. Mccormick, Jr.
Also filed as: MCCORMICK JAMES E · MCCORMICK JR JAMES E · MCCORMICK JR JAMES EARL
16 granted patents·4 pending applications·264 citations·filing 2000–2019
93Inventor score
Files withHEWLETT PACKARD DEVELOPMENT CO7HEWLETT PACKARD CO3INTEL CORP3MCCORMICK JR JAMES E2MCCORMICK JR JAMES EARL2
Top patents by PatentIndex Score
20 records- 0193US6721875B1Method and apparatus for implementing a single-syllable IP-relative branch instruction and a long IP-relative branch instruction in a processor which fetches instructions in bundle formHEWLETT PACKARD DEVELOPMENT CO·Filed 2000·Granted Apr 13, 2004·84 cites·13 claims
- 0288US10346177B2Boot process with parallel memory initializationINTEL CORP·Filed 2016·Granted Jul 9, 2019·6 cites·19 claims
- 0383US6351796B1Methods and apparatus for increasing the efficiency of a higher level cache by selectively performing writes to the higher level cacheHEWLETT PACKARD CO·Filed 2000·Granted Feb 26, 2002·53 cites·20 claims
- 0479US11641326B2Shared memory mesh for switchingINTEL CORP·Filed 2019·Granted May 2, 2023·3 cites·22 claims
- 0575US7747844B2Acquiring instruction addresses associated with performance monitoring eventsHEWLETT PACKARD DEVELOPMENT CO·Filed 2005·Granted Jun 29, 2010·9 cites·30 claims
- 0675US6678817B1Method and apparatus for fetching instructions from the memory subsystem of a mixed architecture processor into a hardware emulation engineHEWLETT PACKARD DEVELOPMENT CO·Filed 2000·Granted Jan 13, 2004·23 cites·1 claims
- 0774US6629167B1Pipeline decoupling buffer for handling early data and late dataHEWLETT PACKARD DEVELOPMENT CO·Filed 2000·Granted Sep 30, 2003·20 cites·21 claims
- 0872US8443171B2Run-time updating of prediction hint instructionsMORRIS DALE·Filed 2004·Granted May 14, 2013·17 cites·28 claims
- 0972US6470438B1Methods and apparatus for reducing false hits in a non-tagged, n-way cacheHEWLETT PACKARD CO·Filed 2000·Granted Oct 22, 2002·16 cites·14 claims
- 1067US9442861B2System and method for out-of-order prefetch instructions in an in-order pipelineMCCORMICK JR JAMES EARL·Filed 2011·Granted Sep 13, 2016·3 cites·19 claims
- 1166US6516388B1Method and apparatus for reducing cache pollutionHEWLETT PACKARD CO·Filed 2000·Granted Feb 4, 2003·12 cites·20 claims
- 1265US6647487B1Apparatus and method for shift register rate control of microprocessor instruction prefetchesHEWLETT PACKARD DEVELOPMENT CO·Filed 2000·Granted Nov 11, 2003·12 cites·11 claims
- 1360US6622209B2Use of non-count data and index hashing to reduce false hits in a non-tagged, n-way cacheHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Sep 16, 2003·6 cites·8 claims
- 1447US10261909B2Speculative cache modificationINTEL CORP·Filed 2015·Granted Apr 16, 2019·0 cites·18 claims
- 1546US2004049667A1Method of patching compiled and linked program code comprising instructions which are grouped into bundlesFiled 2003·Application pending·0 cites
- 1646US2004095965A1Routing of wires carrying single-syllable IP-relative branch instructions and long IP-relative branch instructionsFiled 2003·Application pending·0 cites
- 1744US7356674B2Method and apparatus for fetching instructions from the memory subsystem of a mixed architecture processor into a hardware emulation engineHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Apr 8, 2008·0 cites·15 claims
- 1840US9092346B2Speculative cache modificationMCCORMICK JR JAMES E·Filed 2011·Granted Jul 28, 2015·0 cites·25 claims
- 1936US2014208075A1Systems and method for unblocking a pipeline with spontaneous load deferral and conversion to prefetchMCCORMICK JR JAMES EARL·Filed 2011·Application pending·0 cites
- 2035US2013159679A1Providing Hint Register Storage For A ProcessorMCCORMICK JR JAMES E·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →