Inventor · disambiguated record
Andrew Bellis
Also filed as: BELLIS ANDREW · BELLIS ANDREW J
11 granted patents·227 citations·filing 2003–2011
91Inventor score
Top patents by PatentIndex Score
11 records- 0196US7593273B2Read-leveling implementations for DDR3 applications on an FPGAALTERA CORP·Filed 2007·Granted Sep 22, 2009·44 cites·22 claims
- 0296US7590008B1PVT compensated auto-calibration scheme for DDR3ALTERA CORP·Filed 2007·Granted Sep 15, 2009·58 cites·25 claims
- 0395US7983094B1PVT compensated auto-calibration scheme for DDR3ALTERA CORP·Filed 2009·Granted Jul 19, 2011·49 cites·20 claims
- 0488US7928770B1I/O block for high performance memory interfacesALTERA CORP·Filed 2007·Granted Apr 19, 2011·22 cites·21 claims
- 0573US7589556B1Dynamic control of memory interface timingALTERA CORP·Filed 2007·Granted Sep 15, 2009·7 cites·27 claims
- 0672US7990786B2Read-leveling implementations for DDR3 applications on an FPGAALTERA CORP·Filed 2009·Granted Aug 2, 2011·6 cites·10 claims
- 0772US6828822B1Apparatus and methods for shared memory interfaces in programmable logic devicesALTERA CORP·Filed 2003·Granted Dec 7, 2004·18 cites·42 claims
- 0870US7249222B1Prefetching data based on predetermined criteriaALTERA CORP·Filed 2004·Granted Jul 24, 2007·16 cites·21 claims
- 0968US7990783B1Postamble timing for DDR memoriesALTERA CORP·Filed 2011·Granted Aug 2, 2011·3 cites·20 claims
- 1063US7876630B1Postamble timing for DDR memoriesALTERA CORP·Filed 2007·Granted Jan 25, 2011·4 cites·20 claims
- 1146US9515880B1Integrated circuits with clock selection circuitryVENKATA RAMANAND·Filed 2011·Granted Dec 6, 2016·0 cites·21 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →