Inventor · disambiguated record
Michael A. Woodmansee
Also filed as: WOODMANSEE MICHAEL · WOODMANSEE MICHAEL A · WOODMANSEE MICHAEL ASBURY
15 granted patents·4 pending applications·346 citations·filing 1990–2024
94Inventor score
Top patents by PatentIndex Score
19 records- 0193US5430884AScalar/vector processorCRAY RESEARCH INC·Filed 1990·Granted Jul 4, 1995·131 cites·11 claims
- 0290US12141268B2Secure execution for multiple processor devices using trusted executing environmentsNVIDIA CORP·Filed 2021·Granted Nov 12, 2024·2 cites·23 claims
- 0379US7685371B1Hierarchical flush barrier mechanism with deadlock avoidanceNVIDIA CORP·Filed 2006·Granted Mar 23, 2010·9 cites·11 claims
- 0473US5640524AMethod and apparatus for chaining vector instructionsCRAY RESEARCH INC·Filed 1995·Granted Jun 17, 1997·41 cites·8 claims
- 0573US2025117473A1Secure execution for multiple processor devices using trusted executing environmentsNVIDIA CORP·Filed 2024·Application pending·0 cites
- 0671US7631152B1Determining memory flush states for selective heterogeneous memory flushesNVIDIA CORP·Filed 2006·Granted Dec 8, 2009·5 cites·19 claims
- 0770US5745721APartitioned addressing apparatus for vector/scalar registersCRAY RESEARCH INC·Filed 1995·Granted Apr 28, 1998·34 cites·2 claims
- 0870US2025158813A1Implementing trusted executing environments across multiple processor devicesNVIDIA CORP·Filed 2024·Application pending·0 cites
- 0965US5659706AVector/scalar processor with simultaneous processing and instruction cache fillingCRAY RESEARCH INC·Filed 1995·Granted Aug 19, 1997·28 cites·1 claims
- 1063US12219057B2Implementing trusted executing environments across multiple processor devicesNVIDIA CORP·Filed 2021·Granted Feb 4, 2025·0 cites·23 claims
- 1156US5544337AVector processor having registers for control by vector resistersCRAY RESEARCH INC·Filed 1995·Granted Aug 6, 1996·33 cites·7 claims
- 1253US5623650AMethod of processing a sequence of conditional vector IF statementsCRAY RESEARCH INC·Filed 1995·Granted Apr 22, 1997·28 cites·4 claims
- 1352US5706490AMethod of processing conditional branch instructions in scalar/vector processorCRAY RESEARCH INC·Filed 1995·Granted Jan 6, 1998·15 cites·2 claims
- 1451US2023297696A1Confidential computing using parallel processors with code and data protectionNVIDIA CORP·Filed 2023·Application pending·0 cites
- 1549US2014136793A1System and method for reduced cache modeNVIDIA CORP·Filed 2012·Application pending·0 cites
- 1646US9946658B2Memory interface design having controllable internal and external interfaces for bypassing defective memoryNVIDIA CORP·Filed 2013·Granted Apr 17, 2018·0 cites·5 claims
- 1742US10452566B2Storing secure state information in translation lookaside buffer cache linesNVIDIA CORP·Filed 2015·Granted Oct 22, 2019·0 cites·24 claims
- 1841US5598547AVector processor having functional unit paths of differing pipeline lengthsCRAY RESEARCH INC·Filed 1995·Granted Jan 28, 1997·14 cites·2 claims
- 1939US5717881AData processing system for processing one and two parcel instructionsCRAY RESEARCH INC·Filed 1995·Granted Feb 10, 1998·6 cites·1 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →