Inventor · disambiguated record
Andrew Mark Nightingale
Also filed as: NIGHTINGALE ANDREW M · NIGHTINGALE ANDREW MARK
9 granted patents·1 pending application·167 citations·filing 2001–2008
88Inventor score
Top patents by PatentIndex Score
10 records- 0190US6876941B2Testing compliance of a device with a bus protocolADVANCED RISC MACH LTD·Filed 2002·Granted Apr 5, 2005·91 cites·18 claims
- 0278US7099813B2Simulating program instruction execution and hardware device operationADVANCED RISC MACH LTD·Filed 2002·Granted Aug 29, 2006·31 cites·20 claims
- 0368US7366650B2Software and hardware simulationADVANCED RISC MACH LTD·Filed 2002·Granted Apr 29, 2008·15 cites·16 claims
- 0460US7979822B2Apparatus and method for performing a sequence of verification tests to verify a design of a data processing systemADVANCED RISC MACH LTD·Filed 2008·Granted Jul 12, 2011·4 cites·18 claims
- 0559US7240268B2Test component and method of operation thereofADVANCED RISC MACH LTD·Filed 2003·Granted Jul 3, 2007·9 cites·73 claims
- 0658US7627462B2Hardware simulation using a test scenario managerADVANCED RISC MACH LTD·Filed 2001·Granted Dec 1, 2009·7 cites·27 claims
- 0753US7856346B2Emulating multiple bus used within a data processing systemADVANCED RISC MACH LTD·Filed 2002·Granted Dec 21, 2010·4 cites·18 claims
- 0852US8180620B2Apparatus and method for performing hardware and software co-verification testingNIGHTINGALE ANDREW MARK·Filed 2004·Granted May 15, 2012·6 cites·51 claims
- 0946US2009070493A1Interconnect component and device configuration generationADVANCED RISC MACH LTD·Filed 2008·Application pending·0 cites
- 1044US7761280B2Data processing apparatus simulation by generating anticipated timing information for bus data transfersADVANCED RISC MACH LTD·Filed 2004·Granted Jul 20, 2010·0 cites·46 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →