Inventor · disambiguated record
Fred Gruner
Also filed as: GRUNER FRED
25 granted patents·533 citations·filing 1996–2016
97Inventor score
Top patents by PatentIndex Score
25 records- 0198US6880049B2Sharing a second tier cache memory in a multi-processorJUNIPER NETWORKS INC·Filed 2002·Granted Apr 12, 2005·139 cites·23 claims
- 0295US10289469B2Reliability enhancement utilizing speculative execution systems and methodsNVIDIA CORP·Filed 2016·Granted May 14, 2019·45 cites·44 claims
- 0395US6754774B2Streaming output engine facilitating data transfers between application engines and memoryJUNIPER NETWORKS INC·Filed 2002·Granted Jun 22, 2004·126 cites·46 claims
- 0490US6901482B2Managing ownership of a full cache line using a store-create operationJUNIPER NETWORKS INC·Filed 2002·Granted May 31, 2005·40 cites·24 claims
- 0589US8321761B1ECC bits used as additional register file storageGRUNER FRED·Filed 2009·Granted Nov 27, 2012·9 cites·19 claims
- 0689US8301980B2Error detection and correction for external DRAMGRUNER FRED·Filed 2009·Granted Oct 30, 2012·19 cites·25 claims
- 0787US6839808B2Processing cluster having multiple compute engines and shared tier one cachesJUNIPER NETWORKS INC·Filed 2001·Granted Jan 4, 2005·35 cites·41 claims
- 0877US7068603B2Cross-bar switchJUNIPER NETWORKS INC·Filed 2001·Granted Jun 27, 2006·13 cites·40 claims
- 0976US6901489B2Streaming input engine facilitating data transfers between application engines and memoryJUNIPER NETWORKS INC·Filed 2002·Granted May 31, 2005·12 cites·45 claims
- 1075US6901488B2Compute engine employing a coprocessorJUNIPER NETWORKS INC·Filed 2002·Granted May 31, 2005·11 cites·44 claims
- 1165US8190974B2Error detection and correction for external DRAMGRUNER FRED·Filed 2009·Granted May 29, 2012·3 cites·20 claims
- 1265US6032278AMethod and apparatus for performing scan testingINTEL CORP·Filed 1996·Granted Feb 29, 2000·26 cites·13 claims
- 1363US9490847B2Error detection and correction for external DRAMNVIDIA CORP·Filed 2012·Granted Nov 8, 2016·2 cites·20 claims
- 1463US8250439B1ECC bits used as additional register file storageGRUNER FRED·Filed 2009·Granted Aug 21, 2012·2 cites·20 claims
- 1563US7170902B2Cross-bar switch incorporating a sink port with retry capabilityJUNIPER NETWORKS INC·Filed 2001·Granted Jan 30, 2007·4 cites·18 claims
- 1663US7123585B2Cross-bar switch with bandwidth allocationJUNIPER NETWORKS INC·Filed 2001·Granted Oct 17, 2006·4 cites·32 claims
- 1759US6862669B2First tier cache memory preventing stale data storageJUNIPER NETWORKS INC·Filed 2002·Granted Mar 1, 2005·2 cites·16 claims
- 1858US6920529B2Transferring data between cache memory and a media access controllerJUNIPER NETWORKS INC·Filed 2002·Granted Jul 19, 2005·2 cites·55 claims
- 1955US7733905B2Cross-bar switch having bandwidth allocationJUNIPER NETWORKS INC·Filed 2007·Granted Jun 8, 2010·0 cites·10 claims
- 2054US7813364B2Cross-bar switch incorporating a sink port with retry capabilityJUNIPER NETWORKS INC·Filed 2006·Granted Oct 12, 2010·0 cites·11 claims
- 2150US5978944AMethod and apparatus for scan testing dynamic circuitsINTEL CORP·Filed 1997·Granted Nov 2, 1999·15 cites·12 claims
- 2245US9734545B2Software methods in a GPUDULUK JR JEROME F·Filed 2010·Granted Aug 15, 2017·0 cites·21 claims
- 2338US6684322B1Method and system for instruction length decodeINTEL CORP·Filed 1999·Granted Jan 27, 2004·9 cites·23 claims
- 2437US7213129B1Method and system for a two stage pipelined instruction decode and alignment using previous instruction lengthINTEL CORP·Filed 1999·Granted May 1, 2007·9 cites·16 claims
- 2536US5872795AMethod and apparatus for scan testing of multi-phase logicINTEL CORP·Filed 1997·Granted Feb 16, 1999·6 cites·16 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →