Inventor · disambiguated record
Kavitha Chaturvedula
Also filed as: CHATURVEDULA KAVITHA
6 granted patents·4 pending applications·149 citations·filing 2003–2016
82Inventor score
Top patents by PatentIndex Score
10 records- 0195US7895546B2Statistical design closureLSI CORP·Filed 2007·Granted Feb 22, 2011·100 cites·20 claims
- 0280US7082584B2Automated analysis of RTL code containing ASIC vendor rulesLSI LOGIC CORP·Filed 2003·Granted Jul 25, 2006·40 cites·4 claims
- 0363US7844929B2Optimizing test code generation for verification environmentLSI CORP·Filed 2008·Granted Nov 30, 2010·4 cites·20 claims
- 0459US7594201B2Enhanced method of optimizing multiplex structures and multiplex control structures in RTL codeLSI CORP·Filed 2006·Granted Sep 22, 2009·2 cites·28 claims
- 0548US8001497B2Control signal source replicationLSI CORP·Filed 2008·Granted Aug 16, 2011·0 cites·20 claims
- 0647US7086015B2Method of optimizing RTL code for multiplex structuresLSI LOGIC CORP·Filed 2004·Granted Aug 1, 2006·3 cites·6 claims
- 0746US2010217564A1Advanced physical simulatorLAHNER JUERGEN K·Filed 2009·Application pending·0 cites
- 0839US2007079266A1Method and computer program for analysis of an integrated circuit design to identify and resolve a problematic structure characterized by multiple rule violations using a design closure knowledge base and a physical design databaseLSI LOGIC CORP·Filed 2005·Application pending·0 cites
- 0936US2017212579A1Storage Device With Power Management ThrottlingAVAGO TECHNOLOGIES GENERAL IP·Filed 2016·Application pending·0 cites
- 1036US2016216758A1PCI Express Device With Early Low Power StateAVAGO TECHNOLOGIES GENERAL IP·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →