Inventor · disambiguated record
Travis Bradfield
Also filed as: BRADFIELD TRAVIS A · BRADFIELD TRAVIS ALISTER
8 granted patents·3 pending applications·66 citations·filing 2001–2012
85Inventor score
Top patents by PatentIndex Score
11 records- 0177US6922817B2System and method for achieving timing closure in fixed placed designs after implementing logic changesLSI LOGIC CORP·Filed 2003·Granted Jul 26, 2005·32 cites·18 claims
- 0271US7719368B1Configurable reset circuit for a phase-locked loopAGERE SYSTEMS INC·Filed 2008·Granted May 18, 2010·11 cites·21 claims
- 0361US6886147B2Method, system, and product for achieving optimal timing in a data path that includes variable delay lines and coupled endpointsLSI LOGIC CORP·Filed 2002·Granted Apr 26, 2005·9 cites·39 claims
- 0456US7085903B2Method, apparatus, and program for improving data mirroring performance in a SCSI topologyLSI CORP·Filed 2003·Granted Aug 1, 2006·5 cites·20 claims
- 0553US7107375B2Method for improving selection performance by using an arbitration elimination scheme in a SCSI topologyLSI LOGIC CORP·Filed 2003·Granted Sep 12, 2006·3 cites·18 claims
- 0650US6566939B1Programmable glitch filterLSI LOGIC CORP·Filed 2001·Granted May 20, 2003·6 cites·18 claims
- 0745US7076577B2Pipeline SCSI nexus associativity circuitLSI LOGIC CORP·Filed 2003·Granted Jul 11, 2006·0 cites·23 claims
- 0843US2006031603A1Multi-threaded/multi-issue DMA engine data transfer systemBRADFIELD TRAVIS A·Filed 2004·Application pending·0 cites
- 0942US2006090015A1Pipelined circuit for tag availability with multi-threaded direct memory access (DMA) activityBRADFIELD TRAVIS A·Filed 2004·Application pending·0 cites
- 1039US2013219088A1Configurable prioritization of data transmission in a data storage topologyRAWE LAWRENCE J·Filed 2012·Application pending·0 cites
- 1130US7236051B2Programmable glitch filterLSI CORP·Filed 2003·Granted Jun 26, 2007·0 cites·8 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →