Inventor · disambiguated record
Roland A. Bechade
Also filed as: BECHADE ROLAND · BECHADE ROLAND A · BECHADE ROLAND ALBERT
24 granted patents·434 citations·filing 1985–1998
96Inventor score
Top patents by PatentIndex Score
24 records- 0188US5272729AClock signal latency elimination networkIBM·Filed 1991·Granted Dec 21, 1993·142 cites·24 claims
- 0281US5789966ADistributed multiplexerIBM·Filed 1996·Granted Aug 4, 1998·39 cites·10 claims
- 0380US4912339APass gate multiplexerIBM·Filed 1988·Granted Mar 27, 1990·26 cites·15 claims
- 0474US5805491AFast 4-2 carry save adder using multiplexer logicIBM·Filed 1997·Granted Sep 8, 1998·29 cites·7 claims
- 0563US5511016AMethod for store rounding and circuit thereforIBM·Filed 1994·Granted Apr 23, 1996·39 cites·14 claims
- 0650US5923574AOptimized, combined leading zeros counter and shifterIBM·Filed 1996·Granted Jul 13, 1999·23 cites·9 claims
- 0750US5568410AMethod and apparatus for determining the amount of leading zeros or ones in a binary data fieldIBM·Filed 1994·Granted Oct 22, 1996·21 cites·18 claims
- 0845US6003059ACarry select adder using two level selectorsIBM·Filed 1997·Granted Dec 14, 1999·17 cites·15 claims
- 0945US5841683ALeast significant bit and guard bit extractorIBM·Filed 1996·Granted Nov 24, 1998·20 cites·8 claims
- 1043US5430387ATransition-controlled off-chip driverIBM·Filed 1992·Granted Jul 4, 1995·10 cites·16 claims
- 1142US4766565AArithmetic logic circuit having a carry generatorIBM·Filed 1986·Granted Aug 23, 1988·11 cites·15 claims
- 1240US5179294AProcess independent digital clock signal shaping networkIBM·Filed 1991·Granted Jan 12, 1993·9 cites·15 claims
- 1338US4742019AMethod for forming aligned interconnections between logic stagesIBM·Filed 1985·Granted May 3, 1988·9 cites·10 claims
- 1436US5283755AMultiplier employing carry select or carry look-ahead adders in hierarchical tree configurationIBM·Filed 1993·Granted Feb 1, 1994·8 cites·26 claims
- 1536US5278456AProcess independent digital clock signal shaping networkIBM·Filed 1993·Granted Jan 11, 1994·9 cites·4 claims
- 1635US4982357APlural dummy select chain logic synthesis networkIBM·Filed 1989·Granted Jan 1, 1991·6 cites·14 claims
- 1734US6134576AParallel adder with independent odd and even sum bit generation cellsMENTOR GRAPHICS CORP·Filed 1998·Granted Oct 17, 2000·7 cites·15 claims
- 1831US5905428AN-bit comparator using count leading 1 circuitsIBM·Filed 1997·Granted May 18, 1999·2 cites·20 claims
- 1931US5745744AHigh speed mask generation using selection logicIBM·Filed 1995·Granted Apr 28, 1998·2 cites·31 claims
- 2030US6108678AMethod and apparatus to detect a floating point mantissa of all zeros or all onesMENTOR GRAPHICS CORP·Filed 1998·Granted Aug 22, 2000·0 cites·18 claims
- 2130US5975749AZero and one detection chain for a carry select adderIBM·Filed 1997·Granted Nov 2, 1999·0 cites·19 claims
- 2229US6148315AFloating point unit having a unified adder-shifter designMENTOR GRAPHICS CORP·Filed 1998·Granted Nov 14, 2000·0 cites·11 claims
- 2327US4768161ADigital binary array multipliers using inverting full addersIBM·Filed 1986·Granted Aug 30, 1988·2 cites·37 claims
- 2421US6415008B1Digital signal multiplierFiled 1998·Granted Jul 2, 2002·3 cites·23 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →