Inventor · disambiguated record
Peter Verwegen
Also filed as: VERWEGEN PETER
5 granted patents·31 citations·filing 1998–2014
78Inventor score
Files withIBM5
Top patents by PatentIndex Score
5 records- 0181US9536030B2Optimization of integrated circuit physical designIBM·Filed 2014·Granted Jan 3, 2017·8 cites·20 claims
- 0275US7560964B2Latch and clock structures for enabling race-reduced MUX scan and LSSD co-compatibilityIBM·Filed 2005·Granted Jul 14, 2009·7 cites·19 claims
- 0370US7482851B2Latch and clock structures for enabling race-reduced mux scan and LSSD co-compatibilityIBM·Filed 2007·Granted Jan 27, 2009·5 cites·11 claims
- 0446US7401278B2Edge-triggered master + LSSD slave binary latchIBM·Filed 2004·Granted Jul 15, 2008·4 cites·9 claims
- 0536US6147546AZero volt/zero current fuse arrangementIBM·Filed 1998·Granted Nov 14, 2000·7 cites·3 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →