Inventor · disambiguated record
Sailesh Chittipeddi
Also filed as: CHITTIPEDDI SAILESH
64 granted patents·7 pending applications·2,076 citations·filing 1990–2013
99Inventor score
Files withLUCENT TECHNOLOGIES INC27AGERE SYST GUARDIAN CORP16AGERE SYSTEMS INC15AT & T BELL LAB3CHITTIPEDDI SAILESH2
Top patents by PatentIndex Score
71 records- 0197US5918116AProcess for forming gate oxides possessing different thicknesses on a semiconductor substrateLUCENT TECHNOLOGIES INC·Filed 1997·Granted Jun 29, 1999·232 cites·25 claims
- 0294US5751065AIntegrated circuit with active devices under bond padsLUCENT TECHNOLOGIES INC·Filed 1995·Granted May 12, 1998·185 cites·11 claims
- 0393US5986343ABond pad design for integrated circuitsLUCENT TECHNOLOGIES INC·Filed 1998·Granted Nov 16, 1999·126 cites·12 claims
- 0493US5573965AMethod of fabricating semiconductor devices and integrated circuits using sidewall spacer technologyLUCENT TECHNOLOGIES INC·Filed 1993·Granted Nov 12, 1996·114 cites·17 claims
- 0592US7952206B2Solder bump structure for flip chip semiconductor devices and method of manufacture thereforeAGERE SYSTEMS INC·Filed 2006·Granted May 31, 2011·20 cites·10 claims
- 0692US6790757B1Wire bonding method for copper interconnects in semiconductor devicesAGERE SYSTEMS INC·Filed 1999·Granted Sep 14, 2004·111 cites·16 claims
- 0792US6773994B2CMOS vertical replacement gate (VRG) transistorsAGERE SYSTEMS INC·Filed 2001·Granted Aug 10, 2004·65 cites·14 claims
- 0890US5972179ASilicon IC contacts using composite TiN barrier layerLUCENT TECHNOLOGIES INC·Filed 1997·Granted Oct 26, 1999·114 cites·11 claims
- 0986US5147820ASilicide formation on polysiliconAT & T BELL LAB·Filed 1991·Granted Sep 15, 1992·68 cites·15 claims
- 1083US6472304B2Wire bonding to copperAGERE SYSTEMS INC·Filed 2001·Granted Oct 29, 2002·35 cites·3 claims
- 1183US5965903ADevice and method of manufacture for an integrated circuit having a BIST circuit and bond pads incorporated thereinLUCENT TECHNOLOGIES INC·Filed 1998·Granted Oct 12, 1999·61 cites·21 claims
- 1282US8507317B2Solder bump structure for flip chip semiconductor devices and method of manufacturing thereforeBACHMAN MARK A·Filed 2011·Granted Aug 13, 2013·5 cites·7 claims
- 1381US6387772B1Method for forming trench capacitors in SOI substratesAGERE SYST GUARDIAN CORP·Filed 2000·Granted May 14, 2002·25 cites·11 claims
- 1481US5891784ATransistor fabrication methodLUCENT TECHNOLOGIES INC·Filed 1995·Granted Apr 6, 1999·70 cites·6 claims
- 1580US7563669B2Integrated circuit with a trench capacitor structure and method of manufactureAGERE SYSTEMS INC·Filed 2006·Granted Jul 21, 2009·9 cites·7 claims
- 1680US6556409B1Integrated circuit including ESD circuits for a multi-chip module and a method thereforAGERE SYSTEMS INC·Filed 2000·Granted Apr 29, 2003·28 cites·20 claims
- 1780US6503793B1Method for concurrently forming an ESD protection device and a shallow trench isolation regionAGERE SYSTEMS INC·Filed 2001·Granted Jan 7, 2003·27 cites·20 claims
- 1880US6417087B1Process for forming a dual damascene bond pad structure over active circuitryAGERE SYST GUARDIAN CORP·Filed 1999·Granted Jul 9, 2002·60 cites·20 claims
- 1980US6265890B1In-line non-contact depletion capacitance measurement method and apparatusLUCENT TECHNOLOGIES INC·Filed 1999·Granted Jul 24, 2001·44 cites·8 claims
- 2080US6207547B1Bond pad design for integrated circuitsLUCENT TECHNOLOGIES INC·Filed 1999·Granted Mar 27, 2001·48 cites·8 claims
- 2178US6838769B1Dual damascene bond pad structure for lowering stress and allowing circuitry under padsAGERE SYSTEMS INC·Filed 1999·Granted Jan 4, 2005·51 cites·23 claims
- 2278US6187658B1Bond pad for a flip chip package, and method of forming the sameLUCENT TECHNOLOGIES INC·Filed 2000·Granted Feb 13, 2001·22 cites·8 claims
- 2377US6358785B1Method for forming shallow trench isolation structuresLUCENT TECHNOLOGIES INC·Filed 2000·Granted Mar 19, 2002·26 cites·18 claims
- 2476US6384452B1Electrostatic discharge protection device with monolithically formed resistor-capacitor portionAGERE SYST GUARDIAN CORP·Filed 2000·Granted May 7, 2002·23 cites·13 claims
- 2575US6017787AIntegrated circuit with twin tubLUCENT TECHNOLOGIES INC·Filed 1996·Granted Jan 25, 2000·47 cites·9 claims
- 2669US6552381B2Trench capacitors in SOI substratesAGERE SYSTEMS INC·Filed 2002·Granted Apr 22, 2003·12 cites·15 claims
- 2769US6191017B1Method of forming a multi-layered dual-polysilicon structureLUCENT TECHNOLOGIES INC·Filed 1999·Granted Feb 20, 2001·28 cites·25 claims
- 2868US6319837B1Technique for reducing dishing in Cu-based interconnectsAGERE SYST GUARDIAN CORP·Filed 2000·Granted Nov 20, 2001·15 cites·19 claims
- 2967US6246325B1Distributed communications system for reducing equipment down-timeAGERE SYST GUARDIAN CORP·Filed 1999·Granted Jun 12, 2001·48 cites·17 claims
- 3067US6087732ABond pad for a flip-chip packageLUCENT TECHNOLOGIES INC·Filed 1998·Granted Jul 11, 2000·27 cites·14 claims
- 3162US6426263B1Method for making a merged contact window in a transistor to electrically connect the gate to either the source or the drainAGERE SYST GUARDIAN CORP·Filed 2000·Granted Jul 30, 2002·10 cites·13 claims
- 3261US6628001B1Integrated circuit die having alignment marks in the bond pad region and method of manufacturing sameAGERE SYSTEMS INC·Filed 2002·Granted Sep 30, 2003·12 cites·18 claims
- 3361US6500729B1Method for reducing dishing related issues during the formation of shallow trench isolation structuresAGERE SYST GUARDIAN CORP·Filed 2000·Granted Dec 31, 2002·10 cites·19 claims
- 3461US6455418B1Barrier for copper metallizationAGERE SYST GUARDIAN CORP·Filed 2000·Granted Sep 24, 2002·8 cites·6 claims
- 3559US6538283B1Silicon-on-insulator (SOI) semiconductor structure with additional trench including a conductive layerLUCENT TECHNOLOGIES INC·Filed 2000·Granted Mar 25, 2003·9 cites·17 claims
- 3659US6482694B2Semiconductor device structure including a tantalum pentoxide layer sandwiched between silicon nitride layersAGERE SYSTEMS INC·Filed 2001·Granted Nov 19, 2002·5 cites·11 claims
- 3758US6288449B1Barrier for copper metallizationAGERE SYST GUARDIAN CORP·Filed 1998·Granted Sep 11, 2001·19 cites·5 claims
- 3857US6706603B2Method of forming a semiconductor deviceAGERE SYSTEMS INC·Filed 2001·Granted Mar 16, 2004·7 cites·26 claims
- 3957US6294807B1Semiconductor device structure including a tantalum pentoxide layer sandwiched between silicon nitride layersAGERE SYST GUARDIAN CORP·Filed 1999·Granted Sep 25, 2001·17 cites·5 claims
- 4056US5045486ATransistor fabrication methodAT & T BELL LAB·Filed 1990·Granted Sep 3, 1991·26 cites·2 claims
- 4155US6078035AIntegrated circuit processing utilizing microwave radiationLUCENT TECHNOLOGIES INC·Filed 1995·Granted Jun 20, 2000·20 cites·19 claims
- 4253US5807760AMethod of despositing an aluminum-rich layerLUCENT TECHNOLOGIES INC·Filed 1996·Granted Sep 15, 1998·14 cites·7 claims
- 4352US6313025B1Process for manufacturing an integrated circuit including a dual-damascene structure and an integrated circuitAGERE SYST GUARDIAN CORP·Filed 1999·Granted Nov 6, 2001·17 cites·18 claims
- 4452US2014015127A1Contact support pillar structure for flip chip semiconductor devices and method of manufacture thereforeAGERE SYSTEMS LLC·Filed 2013·Application pending·0 cites
- 4551US6762087B1Process for manufacturing an integrated circuit including a dual-damascene structure and a capacitorAGERE SYSTEMS INC·Filed 2000·Granted Jul 13, 2004·4 cites·8 claims
- 4651US5589416AProcess for forming integrated capacitorsLUCENT TECHNOLOGIES INC·Filed 1995·Granted Dec 31, 1996·16 cites·5 claims
- 4751US2008280403A1Transistor fabrication methodCHITTIPEDDI SAILESH·Filed 2008·Application pending·0 cites
- 4849US8030199B2Transistor fabrication methodAGERE SYSTEMS INC·Filed 2010·Granted Oct 4, 2011·0 cites·14 claims
- 4949US6365327B1Process for manufacturing in integrated circuit including a dual-damascene structure and an integrated circuitAGERE SYST GUARDIAN CORP·Filed 1999·Granted Apr 2, 2002·14 cites·20 claims
- 5049US5763314AProcess for forming isolation regions in an integrated circuitLUCENT TECHNOLOGIES INC·Filed 1996·Granted Jun 9, 1998·13 cites·15 claims
Showing the top 50 of 71 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →