Inventor · disambiguated record
Frank Worrell
Also filed as: WORRELL FRANK · WORRELL FRANK H · Worrell Frank Henry
30 granted patents·3 pending applications·503 citations·filing 1995–2021
97Inventor score
Top patents by PatentIndex Score
33 records- 0186US9667446B2Condition code approach for comparing rule and packet data that are provided in portionsCAVIUM INC·Filed 2014·Granted May 30, 2017·9 cites·11 claims
- 0285US9544402B2Multi-rule approach to encoding a group of rulesCAVIUM INC·Filed 2013·Granted Jan 10, 2017·8 cites·15 claims
- 0378US5905893AMicroprocessor adapted for executing both a non-compressed fixed length instruction set and a compressed variable length instruction setLSI LOGIC CORP·Filed 1996·Granted May 18, 1999·87 cites·18 claims
- 0477US7797467B2Systems for implementing SDRAM controllers, and buses adapted to include advanced high performance bus featuresLSI CORP·Filed 2006·Granted Sep 14, 2010·7 cites·22 claims
- 0577US5648733AScan compatible 3-state bus controlLSI LOGIC CORP·Filed 1995·Granted Jul 15, 1997·35 cites·6 claims
- 0674US7966431B2Systems for implementing SDRAM controllers, and buses adapted to include advanced high performance bus featuresLSI CORP·Filed 2010·Granted Jun 21, 2011·3 cites·18 claims
- 0773US6728816B1Simple mechanism for guaranteeing in order read data return on a split transaction busLSI LOGIC CORP·Filed 2001·Granted Apr 27, 2004·18 cites·21 claims
- 0871US6412066B2Microprocessor employing branch instruction to set compression modeLSI LOGIC CORP·Filed 2001·Granted Jun 25, 2002·14 cites·23 claims
- 0970US5896519AApparatus for detecting instructions from a variable-length compressed instruction set having extended and non-extended instructionsLSI LOGIC CORP·Filed 1996·Granted Apr 20, 1999·59 cites·20 claims
- 1069US8046505B2Systems for implementing SDRAM controllers, and buses adapted to include advanced high performance bus featuresLSI CORP·Filed 2010·Granted Oct 25, 2011·2 cites·20 claims
- 1168US11729640B2Methods and apparatus for configuring a front end to process multiple sectors with multiple radio frequency framesMARVELL ASIA PTE LTD·Filed 2021·Granted Aug 15, 2023·0 cites·31 claims
- 1267US7069363B1On-chip busLSI LOGIC CORP·Filed 2002·Granted Jun 27, 2006·12 cites·20 claims
- 1367US5867681AMicroprocessor having register dependent immediate decompressionLSI LOGIC CORP·Filed 1996·Granted Feb 2, 1999·52 cites·8 claims
- 1466US5774709AEnhanced branch delay slot handling with single exception program counterLSI LOGIC CORP·Filed 1995·Granted Jun 30, 1998·48 cites·3 claims
- 1565US7681017B2Pseudo pipeline and pseudo pipelined SDRAM controllerLSI CORP·Filed 2006·Granted Mar 16, 2010·3 cites·26 claims
- 1664US9568944B2Distributed timer subsystem across multiple devicesCAVIUM INC·Filed 2014·Granted Feb 14, 2017·1 cites·18 claims
- 1763US6877082B1Central processing unit including address generation system and instruction fetch apparatusLSI LOGIC CORP·Filed 2002·Granted Apr 5, 2005·9 cites·20 claims
- 1862US5794010AMethod and apparatus for allowing execution of both compressed instructions and decompressed instructions in a microprocessorLSI LOGIC CORP·Filed 1996·Granted Aug 11, 1998·41 cites·20 claims
- 1959US6671781B1Data cache store bufferLSI LOGIC CORP·Filed 2000·Granted Dec 30, 2003·6 cites·10 claims
- 2057US6973561B1Processor pipeline stall based on data register statusLSI LOGIC CORP·Filed 2000·Granted Dec 6, 2005·8 cites·22 claims
- 2155US6948054B2Simple branch prediction and misprediction recovery methodLSI LOGIC CORP·Filed 2000·Granted Sep 20, 2005·4 cites·8 claims
- 2253US9928193B2Distributed timer subsystemCAVIUM INC·Filed 2014·Granted Mar 27, 2018·0 cites·9 claims
- 2352US11172379B2Methods and apparatus for configuring a front end to process multiple sectors with multiple radio frequency framesMARVELL ASIA PTE LTD·Filed 2017·Granted Nov 9, 2021·0 cites·23 claims
- 2451US6012138ADynamically variable length CPU pipeline for efficiently executing two instruction setsLSI LOGIC CORP·Filed 1997·Granted Jan 4, 2000·24 cites·9 claims
- 2543US5729482AMicroprocessor shifter using rotation and masking operationsLSI LOGIC CORP·Filed 1995·Granted Mar 17, 1998·16 cites·13 claims
- 2643US2001025337A1Microprocessor including a mode detector for setting compression modeFiled 2001·Application pending·0 cites
- 2743US2007061554A1Branch predictor for a processor and method of predicting a conditional branchLSI LOGIC CORP·Filed 2005·Application pending·0 cites
- 2842US5982194AArithmetic and logic function circuits optimized for datapath layoutLSI LOGIC CORP·Filed 1995·Granted Nov 9, 1999·14 cites·27 claims
- 2942US2003191896A1Data-cache data-pathFiled 2003·Application pending·0 cites
- 3041US6584537B1Data-cache data-pathLSI LOGIC CORP·Filed 2000·Granted Jun 24, 2003·0 cites·18 claims
- 3136US5931941AInterface for a modularized computational unit to a CPULSI LOGIC CORP·Filed 1995·Granted Aug 3, 1999·9 cites·17 claims
- 3235US5784634APipelined CPU with instruction fetch, execution and write back stagesLSI LOGIC CORP·Filed 1997·Granted Jul 21, 1998·7 cites·9 claims
- 3335US5670900AMask decoder circuit optimized for data pathLSI LOGIC CORP·Filed 1995·Granted Sep 23, 1997·7 cites·6 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →