Inventor · disambiguated record
Robert S. Horton
Also filed as: HORTON ROBERT S · HORTON ROBERT SPENCER
24 granted patents·4 pending applications·416 citations·filing 1991–2025
95Inventor score
Top patents by PatentIndex Score
28 records- 0187US6052129AMethod and apparatus for deferred clipping of polygonsIBM·Filed 1997·Granted Apr 18, 2000·107 cites·33 claims
- 0287US5659671AMethod and apparatus for shading graphical images in a data processing systemIBM·Filed 1996·Granted Aug 19, 1997·116 cites·11 claims
- 0385US7480888B1Design structure for facilitating engineering changes in integrated circuitsIBM·Filed 2008·Granted Jan 20, 2009·14 cites·3 claims
- 0482US11800246B2Systems and methods for multispectral landscape mappingLANDSCAN LLC·Filed 2022·Granted Oct 24, 2023·1 cites·41 claims
- 0577US12231785B2Systems and methods for multispectral landscape mappingLANDSCAN LLC·Filed 2023·Granted Feb 18, 2025·0 cites·20 claims
- 0671US9021228B2Managing out-of-order memory command execution from multiple queues while maintaining data coherencyIBM·Filed 2013·Granted Apr 28, 2015·2 cites·12 claims
- 0771US5303340AConcave polygon drawing method and processor for a computer graphics display systemIBM·Filed 1993·Granted Apr 12, 1994·44 cites·25 claims
- 0871US2025193539A1Systems and Methods for Multispectral Landscape MappingLANDSCAN LLC·Filed 2025·Application pending·0 cites
- 0970US9317434B2Managing out-of-order memory command execution from multiple queues while maintaining data coherencyIBM·Filed 2015·Granted Apr 19, 2016·1 cites·10 claims
- 1069US6177944B1Two phase rendering for computer graphicsIBM·Filed 1998·Granted Jan 23, 2001·45 cites·15 claims
- 1168US8060845B2Minimizing impact of design changes for integrated circuit designsHERZL ROBERT D·Filed 2008·Granted Nov 15, 2011·4 cites·6 claims
- 1268US5434967ADecision variable hardware logic and processing methods for graphics display systemIBM·Filed 1992·Granted Jul 18, 1995·33 cites·20 claims
- 1367US8141028B2Structure for identifying and implementing flexible logic block logic for easy engineering changesHERZL ROBERT D·Filed 2008·Granted Mar 20, 2012·4 cites·2 claims
- 1466US9026763B2Managing out-of-order memory command execution from multiple queues while maintaining data coherencyIBM·Filed 2013·Granted May 5, 2015·1 cites·8 claims
- 1564US9319040B2Distributing multiplexing logic to remove multiplexor latency on the output path for variable clock cycle, delayed signalsIBM·Filed 2014·Granted Apr 19, 2016·2 cites·6 claims
- 1659US8341588B2Semiconductor layer forming method and structureHERZL ROBERT D·Filed 2010·Granted Dec 25, 2012·1 cites·19 claims
- 1759US7469312B2Computer system bus bridgeIBM·Filed 2005·Granted Dec 23, 2008·1 cites·11 claims
- 1858US8181148B2Method for identifying and implementing flexible logic block logic for easy engineering changesHERZL ROBERT D·Filed 2008·Granted May 15, 2012·1 cites·17 claims
- 1955US8994424B2Distributing multiplexing logic to remove multiplexor latency on the output path for variable clock cycle, delayed signalsIBM·Filed 2013·Granted Mar 31, 2015·1 cites·15 claims
- 2054US9164908B2Managing out-of-order memory command execution from multiple queues while maintaining data coherencyIBM·Filed 2015·Granted Oct 20, 2015·0 cites·14 claims
- 2153US7757032B2Computer system bus bridgeIBM·Filed 2008·Granted Jul 13, 2010·0 cites·9 claims
- 2251US6525738B1Display list processor for decoupling graphics subsystem operations from a host processorIBM·Filed 1999·Granted Feb 25, 2003·24 cites·33 claims
- 2348US2012167022A1Method and device for identifying and implementing flexible logic block logic for easy engineering changesHERZL ROBERT D·Filed 2012·Application pending·0 cites
- 2447US7065602B2Circuit and method for pipelined insertionIBM·Filed 2003·Granted Jun 20, 2006·0 cites·27 claims
- 2546US2009045839A1Asic logic library of flexible logic blocks and method to enable engineering changeIBM·Filed 2007·Application pending·0 cites
- 2645US2009045836A1Asic logic library of flexible logic blocks and method to enable engineering changeHERZL ROBERT D·Filed 2007·Application pending·0 cites
- 2744US7206886B2Data ordering translation between linear and interleaved domains at a bus interfaceIBM·Filed 2005·Granted Apr 17, 2007·0 cites·20 claims
- 2843US5309552AProgrammable multi-format display controllerIBM·Filed 1991·Granted May 3, 1994·14 cites·4 claims
Join the waitlist — get patent alerts
Get an alert when Robert S. Horton files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →